搜索资源列表
quantizer
- 这个DCT的源代码Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA
DCT
- altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码，语言是：verilog 性能不错，不过资源消耗有点大，可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
DCT_2D.rar
- 二维DCT，FPGA实现JPEG压缩中的二维DCT,dct
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
dct2
- 这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.
81404621JPEG-DCT
- 基于FPGA的DCT实现源代码,已通过MODELSIM验证。-FPGA based source code of DCT
d1_dct
- FPGA 描述DCT ，希望对大家有用。-the DCT arithetics using fpga
dct
- DCT的FPGA实现，用verilog语言把DCT的快速算法即LOEFFLER算法表示出来。-DCT-FPGA, with the verilog language to the fast DCT algorithm, which is LOEFFLER algorithm that out.
ch3_dct
- fpga dct变换，用以视频压缩和处理图像-fpga dct
dct
- JPEG Compression and Ethernet Communication on an FPGA
dct_verilog
- 用FPGA实现dct变换。verilog语言实现，在quartus9.0中验证，含整个工程-dct transform verilog language in quartus9.0 verify, with the entire project
dct
- 基于FPGA的图像压缩算法程序，自己写的，可以参考一下-FPGA-based image compression algorithm, write your own, you can refer to
DCT8_final
- 二维dct算法的fpga实现及验证，采用VHDL语言编写。-2D-dctThe FPGA realizing algorithm
DCT
- 二维dct算法的 fpga实现及验证，采用VHDL语言编写。-2D-dctThe FPGA realizing algorithm
2dDCT
- 二维dct算法的fpga实现及验证,采用VHDL语言编写。-2D-dct The FPGA realizing algorithm
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
INT_DCT
- Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试，均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.
fpga-jpeg
- 包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程-Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project