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DDS_VERILOG
- 本例给出了DDS的VERIOG的程序事例,可发生正弦\\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \\ cosine wave such as, Adaptation and communications hardware realization!
DDS_VERILOG
- verilog dds 在发生正弦波时，很好的参考代码-verilog dds
dds_verilog
- 产生信号发生器的dds的verilog代码，很好的学习资料，值得学习-Verilog code generated signal generator dds good learning materials, it is worth learning
DDS_VERILOG
- 超级精简的DDS发生器，用VERILOG编写，请参考-Super-streamlined DDS generator with VERILOG preparation, please refer to
DDS_verilog
- 通讯中常用的dds模块的verilog源码打包下载-Communications commonly used in dds module verilog source code package to download
DDS_verilog
- 采用verilog实现了DDS发生器，源码已通过仿真编译已经板级调试，可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.