搜索资源列表
DES.rar
- DES算法的verilog实现,实现了硬件IC对DES的构架,可以直接应用在系统当中。,DES algorithm Verilog realized, the realization of the hardware IC framework of DES, can be directly used in the system.
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
DES
- This is verilog source code for DES(Data Encryption standard) which is used in network security.
aes_thesis_v1.0
- AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
DES
- 在ISE平台上,利用Verilog编程实现数据的DES加密-In the ISE platform, using Verilog programming DES data encryption
DES_Encrypt_Decrypt_Verilog
- DES加密算法的Verilog HDL实现,带模式选择端口,可以实现加密和解密,已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
topic
- DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
des
- des解密加密的verilog源代码其中包含有测试源代码,仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
limited_des
- this DES encryption and decryption code in verilog-this is DES encryption and decryption code in verilog
My_DES3
- a triple-DES (Data Encryption Standard) hardware descr iption in verilog-HDL with testbench
Encrypt_Decrypt(DES)_Verilog
- Encrypt and decrypt DES algorithm in verilog
DES_Triple-DES-IP-Cores
- Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
des_latest.tar
- 利用verilog实现的DES和3DES两种加密算法,其中每个算法又利用了两种实现方式,分别是面积优先和性能优先-Both use DES and 3DES encryption algorithms verilog implementation, which took advantage of each algorithm implemented in two ways, which are the priority and performance priority area
DES_orginal_core
- this a DES encryption code in verilog-this is a DES encryption code in verilog
des
- DES in verilog codes