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CPLDOGRAM
- 摘要: 文中介绍了数字频率计的结构、工作原理及计数方式,给出了基于VHDL语言的频率计系统的行为源描述,讨论了在VHDL的高级综合系统QuartusII的支持下,自顶向下地进行传输模块的设计工程,并给出了系统的仿真波形以及其应用实践。-Abstract : This paper introduces a digital frequency of the structure and working principle and counting, is based on VHDL Frequency
quartusii
- 推荐!!!!!学ASIC相当不错的教程!!!!还是可以看看的-recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!
i2cvhdl
- i2c接口编程试验,quartusII开发-i2c Programming Interface testing, development quartusII
QuartusII_RAM
- 介绍了QUARTUSII中ram的应用,以及基于它的NIOS嵌入式小系统设计-were introduced QUARTUSII ram applications, and based on its small Nios Embedded System Design
QuartusII3.0
- QuartusII 3.0学习教程 ,chm文件,经典-study guides, chm, classic
ref-ualaw
- A率/u率 压缩与解压缩的IP核,。 # 由AHDL语言写成,可在MaxplusII和QuartusII中使用,源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
硬件求解平方根
- 硬件求解平方根源代码加密 (硬件求解平方根的,将license添加到原有的MaxplusII或QuartusII的license中就可以直接使用,但源代码加密。altera提供 )-solving square root of the hardware encryption code (square root of the hardware solution will be added to the original license MaxplusII or Quartus II of the
CrackQII5.1
- altera quartusII v5.1 license
QuartusIIresistance
- 关于quartusII中如何设计上拉电阻的方法.-quartusII on how to design the widening resistance.
VerilogHDLPLI
- Verilog HDL的PLI子程序接口,用于与用户C程序在2个方向上传输数据,可用xilinx ISE,quartusii或modelsim仿真,-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
pic16c57code
- 此代码可用modelsim进行仿真,修改rom之后可用quartusII进行综合,希望你们能对此程序不断完善。-modelsim this code can be used for simulation, After amending rom available quartusII comprehensive and hope that you can constantly improve this procedure.
Crack_QII61_b201
- Altera QuartusII 6.1 的License 生成工具软件。-Altera QuartusII 6.1 License generation of software tools.
quartusII_traffic
- 在quartusII平台开发的一个交通灯的控制程序,并在nios平台上可以使用,所用的芯片是Stratix
my_ip_core
- 在quartusII下用verilog语言自己写的IP核,对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
HDLCControlSystem
- 基于Altera公司NiosII嵌入式处理器开发的一个控制系统模型,用QuartusII和VB完成,利用串口实现了PC与Altera_DE2开发板之间通信,DE2反馈信息,PC进行控制操作。本设计获陕西省06年大学生电子设计大赛二等奖。-based Altera Corporation NiosII embedded processor development of a control system model, QuartusII and use VB completed, Use Seria
Gen_Quartus_Vwf_Mif
- 最大特点:可以从文件中导入数据到mif文件中,从文件中导入数据到vwf文件的输入总线中。 对于在QuartusII中做前期仿真,特别是对算法程序的仿真尤其有用。 自己做的,识货的下一个试试,别忘了顶一个先。 有任何建议和改进意见,请发mail到xyzlty@163.com -greatest features : from paper imported data to mif document, from the paper into data to the i
DDS_VHDL_xzy
- 在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器,芯片是Altera公司的-in EDA software development QuartusII use VHDL DDS signal generator , chip companies are Altera
sobel
- 这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件,可在QuartusII或MaxplisII下综合和仿真,并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测,同时还可以实现其它的图像模块化处理算法,例如高斯滤波,平滑等。-this is my own preparation for the 256 * 256 size of the image segmentation Edge Detection vhd document in the n
baseball
- 用VHDL开发的棒球游戏,可以在QuartusII环境下编译,适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.
Eda1
- 程序在报告中,要 用QuartusII运行,注意从word到运行环境中,可能有个别符号不兼容,重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-e