搜索资源列表
systolic
- 脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器
mybole3
- 对话框和文本，对话框展开和收缩功能，菜单功能，加法器功能。-Dialog box and the text of the dialog box to start and systolic function, menu function, adder function.
ECP-paper
- 体外反搏[Externaleounterpulsati。n]系统是一种由应用计算机控制的、无创伤的机、电、气辅助循环装置〔，，。该装置通过包裹在患者下肢和臀部的密封气囊，以特定模式对肢体加压，从而改变正常血液流场分布，保证在肢体、臀部受压引起血液返流回主动脉瓣处时，正好是主动脉瓣关闭的瞬间，并充分利用心脏舒张期的整个时间，使施加于血管的压力保持足够长，最大限度提高舒张压，保证反搏血流以最充分的时间向缺血器官进行灌注，而又不加重心脏的负荷。另一方面，反搏排气时间的确定保证在下一个心脏收缩期之前解除
health
- 个人健康信息管理系统，健康信息的指标包括身高（Height）、体重（Weight）、血压（收缩压SBP、舒张压DBP）、心跳（Heartbeat）等等,允许用户收集，管理自己和家人的健康和身体状况信息并从中获取医疗帮助-Personal health information management system, health indicators, including information on height (Height), weight (Weight), blood pressure
VLSL-Design-of-High-Performance-Full-search-Block-
- 给出了一种用于H.264变换尺寸全搜索快匹配算法的运动估计电路的改进结构，并完成了VLSI设计。通过脉动阵列和全流水线的设计，达到最高的数据重用率、最小的I/O引脚和100 的硬件计算效率。-An improved architecture for H.264 full-pel motion estimation using variable block size full-search block-matching algorithm is proposed in this paper. To
mpi_matmult
- MPI matrix multiplication with two versions (one is broad cast method and another one is systolic method)
Systolic-Algorithm-for-B-Spline-Patch-Generation.
- Systolic Algorithm for B-Spline Patch Generation
cardiac_moiton_demo
- 一个演示心脏收缩扩张的VC小程序，可以读入参数文件，而控制演示时心脏收缩扩张的快慢频率。-Systolic expansion of a small demo program that can read the parameter file, and the control of cardiac contraction and expansion demonstrates the speed of frequency.
Copy-of-Systolic-Architecture-to-convert-colour-t
- the paper presents efficient colour conversion algorithm for fpga implementations
rsa
- RSA 加解密硬件快速实现算法，基于脉动阵列-RSA enctyption/decryption algrothm, based on systolic array
Systolic_Array
- Multiplier using systolic array
SDRAM-USING
- Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
TABLOO
- Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
XILINX-JTAG-PROGRAMER
- Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
behavioral
- This is a code for systolic multiplier,it can be modified for more lenght in data input
systolic
- 实现QR_RLS算法,基于fpga 的非线性功放的dpd实现-realize QR_RLS
systolic--matrix-inversion
- DSP算法架构及设计，内容为基于systolic的上三角矩阵求逆电路的实现，里面有详尽的MATLAB/SIMULINK 仿真模型，及HDL代码和在modelsim中的仿真程序，非常不错的。-Architecture and design of DSP algorithms, based on systolic upper triangular matrix inverse circuit to achieve detailed MATLAB/SIMULINK model and the HDL
EigenVal_J
- 基于“脉动”结构 求 任意偶数阶实对称阵的特征值，用于MIMO通信反馈信道质量，已经在实际产品实现。( 注：脉动结构只需O(n*log(n))量级运算，高效快速)-"Systolic Arrays" structure based Eigen Value Decomposition
Homework4
- 4x4矩阵乘法，使用pipeline结构，可以在AutoESL中综合出Verilog，并在System Generator中测试通过。-Matrix multification in systolic way for AutoESL synthesis
QR-RLS systolic array
- 基于QR分解的RLS算法,脉动结构，附带数据例子。基于C++语言。