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sanjiaobo
- 利用计数器来实现三角波的程序设计任务,用于信号发生器-Use counters to achieve the triangular wave of program design tasks, for the signal generator
CNT10_T
- 这是同步十进制计数器的源程序,有需要的同学可以参照一下!-This is a source synchronous decimal counter, needy students can refer to you!
bhgfdti
- 含有七人表决器,格雷码变换电路,英文字符显示电路,基本触发器(D和JK),74LS160计数器功能模块,步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
jiaotongdeng
- 1). 用红、绿、黄三色发光二极管作信号灯。主干道为东西向,有红、绿、黄三个灯;支干道为南北向,也有红、绿、黄三个灯。红灯亮禁止通行;绿灯亮允许通行;黄灯亮则给行驶中的车辆有时间停靠到禁行线之外。 2).由于主干道车辆较多而支干道车辆较少,所以主干道绿灯时间较长。当主干道允许通行亮绿灯时,支干道亮红灯。而支干道允许通行亮绿灯时,主干道亮红灯,两者交替重复。主干道每次放行50秒,支干道每次放行30秒。 在每次由亮绿灯变成亮红灯的转换过程中间,需要亮5秒的黄灯作为过渡,以使行驶中的车辆有时间
UART_SUCCESS
- 实现FPGA和上位机的串口通信,里面由波特率发生器,移位寄存器,计数器,detecter,switch,switch_bus等功能块综合而成。-FPGA implementation and the host computer' s serial communication, which by the baud rate generator, shift register, counters, detecter, switch, switch_bus such as function bl
VHDLbh
- 带获胜音乐的拔河游戏机,用计数器 译码器组成-With winning the tug-of-war music video game
t1
- 带清零和重置功能的十进制计数器,可以用LED灯显示结果-Cleared and reset with the decimal counter, can use LED lights display the results
SingleclocksynchronousdesignmetricCNTR
- 用VHDL 设计的单时钟同步十进制可逆计数器的设计-VHDL design using a single clock synchronization decimal CNTR Design
shukongfenpin
- 数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of desig
clock
- 60进制计数器,采用十分简便的方法,能够很快速的完成计数功能。-60 M-ary counter, using a very simple way to very quickly complete the count function.
e3
- 4位可逆计数器:将50MHz的时钟进行 分频后的结果作为时钟控制,根据输入进行条件判断,再通过设置一个四位的向量将结果输出,利用数码管显示在实验板上-CNTR 4: will be conducted at 50MHz clock frequency as the clock after the control conditions to determine the basis of inputs, and then set up a four through the results of th
jishuqi
- 使用VHDL语言实现计数器功能 ……使用VHDL语言实现计数器功能 -Use VHDL language scaler functions……Use VHDL language scaler functions
times
- 计数器,用VHDL实现,先6分频,再10分频,24分频,同时可做万年历-Counter, using VHDL realization frequency first 6 hours, 10 minutes and then the frequency, frequency of 24 minutes, at the same time to do calendar
Led
- 本程序有效的防止了按键的抖动,可以移植于各种需要按键防抖的程序,本程序是功能为按键防抖16进制减法计数器-debounced counter VHDL
DIP_PB_Counter
- 本程序有效的防止了按键的抖动,可以移植于各种需要按键防抖的程序,本程序是功能为按键防抖16进制减法计数器-This procedure prevents the effective jitter keys can be transplanted into a variety of procedures need to Anti-Shake button, the program is anti-shake function for the key 16 counter-band subtract
UniversalRegister
- 普通的缓冲器 这种设计是一个普通的缓冲器,可以做一个直接的缓冲器,也可以做一个双向的转移缓冲器,还可以做一个递增的计数器和递减计数器-Universal Register This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
DVF
- 数控分频器的设计数控分频器 端口定义: CLK:时钟输入 D[7..0]:预置数据 Fout:分频输出 说明: D[7..0]作为8位加1计数器的初值,初值越大,分频输出频率越高,反之越低, -NC NC divider divider port the definition of design: CLK: Clock input D [7 .. 0]: preset data Fout: frequency output that: D [7 .. 0] as
DDSckkc
- 以把直接数字频率合成(DDS)看成这样一种技术,它能用数字值形式的信号控制正弦波的频率。最简单的DDS电路包括一个二进制计数器,一个以等间隔正弦波值进行全波编程的ROM,以及一个数模转换器,用于将存储的正弦波值转换为电压。计数器的时钟频率决定了正弦波的频率,但这 -To the Direct Digital Synthesis (DDS) as such a technology, it can use the digital value of the form of the frequen
Shuma
- 完整的电子钟程序,包含报时、定时、闹表的功能,其中包含了二十四进制,60进制计数器的设计,和顶层文件-Complete procedures for the electronic bell, including the time, from time to time, to make the function table, which contains 24 hexadecimal, 60 hexadecimal counter design, and top-level document
Multichanneldataacquisition
- 多路数据采集,包括八路数据模拟电压测量,计数器,99秒马表-Multi-channel data acquisition, including the eight-way analog voltage measurement data, counters, 99 seconds stopwatch