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Count-display-circuit-design(VHDL)
- 用VHDL语言设计计数显示电路。设计输出为3位BCD码的计数显示电路。由三个模块构成:十进制计数器(BCD_CNT)、分时总线切换电路(SCAN)和七段显示译码器电路(DEC_LED)-VHDL language to count the display circuit. The design output for display circuit 3 BCD count. Consists of three modules: the decimal counter (BCD_CNT), time
VHDL
- 硬件描述语言,关于十进制计数器的,有四位和八位的-Hardware descr iption language, the decimal counter, four and eight
Mode-variable-counter-vhdl
- 模可变计数器 vhdl实现 quartus编译通过-Mode variable counter vhdl achieve quartus compiled by
shuzhizhong(vhdl)
- 数字钟设计 计时计数器用24进制计时电路; 可手动校时,能分别进行时、分的校正; 整点报时; 选做:可设置闹时功能,当计时计到预定时间时,扬声器发出闹铃信号,闹铃时间为4s,并可提前终止闹铃。-Digital clock design
VHDL-simple-examples
- 上传的几个VHDL程序:分别是各种功能计数器;使用列举类型的状态机,四D触发器,通用寄存器,伪随机比特发生器,简单的状态机。-Upload several VHDL program: are the various functions of the counter using the enumerated type state machine, four D flip-flop, the general-purpose registers, pseudo-random bit generato
VHDL-counter-code
- 用WHDL实现计数器的各个模块设计,并用FPGA进行功能验证!-With WHDL counter module design and functional verification using FPGA!
VHDL
- 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290:运算方法编写的290计数器:另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器:用CASE语句 全加器: 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and comp
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器,8位全加器,加1减1计数器,序列检测器,异步清零16位加减可控计数器,数码管扫描程序,双2选1,状态机等基本程序!-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
VHDL
- VHDL初级编程实例:动态扫描显示程序、分频器设计程序、8位移位寄存器、BCD计数器设计(任意进制)等等。-VHDL the primary programming examples: dynamic scanning display program, the divider design process, the 8-bit shift register, BCD counter design (any hex), and so on.
VHDL
- 十进制加减计数器vhdl设计,给学生党最好的借鉴-Decimal addition and subtraction counter VHDL design
VHDL-book3
- D_flipflop:1位D触发器的设计 D_fllipflop_behav:4位D触发器的设计 reg1bit:1位寄存器设计 reg4bit:4位寄存器设计 shiftreg4:一般移位寄存器的设计 ring_shiftreg4:环型移位寄存器的设计 debounce4:消抖电路的设计 clock_pulse:时钟脉冲电路的设计 count3bit_gate:3位计数器的设计 count3bit_behav:3位计数器的设计 mo
VHDL
- 本程序包换一个游戏程序和各种功能的计数器和加法器源程序及波形发生器的代码程序,适合初学者使用-This program replacement a game program and a variety of functions counters and adders and waveform generator source code procedures, suitable for beginners
VHDL
- odule vga_timing ( input wire clk_i, //输入时钟 40MHz input wire reset_i, //输入复位信号 output wire vga_pixel_flag, //输出像素有效 output reg vga_line_o, //输出水平信号 output reg vga_field_o, //输出垂直信号 output reg vga_frame_o //输出帧开始信号 ) //////////
VHDL
- 四选一电路,分钟计数器,三八译码器,先进先出-Four elected a circuit, VHDL procedures VHDL procedures VHDL procedures VHDL program
VHDL-code
- 使用VHDL语言进行门电路,优先编码器,译码器,各进制计数器,数码管显示的编写,在QUARTUS ii上模拟可用-Gates using VHDL language, priority encoder, decoder, each binary counter, write digital display, analogue available on QUARTUS ii
vhdl
- 通过VHDL语言,实现简单的多路选择器、串行加法器、并行加法器、计数器-By VHDL language, a simple multiple-choice, serial adder, parallel adder, counter
vhdl
- 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
VHDL-Programming-Examples
- 分频器、译码器、编码器、计数器、状态机等基本的硬件描述语言代码-The basic hardware divider, decoders, encoders, counters, state machine descr iption language code
piano
- 电子琴 原创 作业 VHDL 采用计数器分频,内含简单儿歌数首,爱迪克EDA实验箱,有数码管与LED显示,采用键盘式输出,两行,中音高音。(Electronic piano original work VHDL, using counter frequency division, contains a few simple nursery rhyme, Edik EDA experimental box, there are digital tube and LED display, usin
he
- 利用VHDL实现判向计数器,并且在数码管上实现显示。可以在XILINX开发板上实现对应功能,仿真也能实现。(The use of VHDL realize the counter counter, and in the digital tube to achieve display. The corresponding function can be implemented on the XILINX development board, and the simulation can also