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VHDL-based-design-of-SPI
- 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous comm
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Pregunta01
- vhdl quartus maquina estados mealy vhdl quartus maquina estados mealy moore vhdl quartus maquina estados mealy moore vhdl quartus maquina estados mealy moore-vhdl quartus maquina estados mealy vhdl quartus maquina estados mealy moore vhdl quartus ma
FIR_IP_lowpass
- 8阶FIR_IP的VHDL代码以及QuartusII的顶层文件-FIR_IP the VHDL code of order 8 and the top-level file QuartusII
lcd
- DE2-70开发板的LCD控制程序，能直接在DE2-70上运行。版本是quartus 9.0-DE2-70 development board of the LCD control procedures can be directly run on the DE2-70. Version of quartus 9.0
BPSK
- 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制，其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
FM
- 在quartus ii下完成的用VHDL语言编写的数字式调频系统-Accomplished in quartus ii the use of VHDL language digital FM system
Sn_Quartus
- Synthesizerr frequency VHDL Quartus 90.
Signal-Generator-VHDL
- 这是基于quartus dds信号发生器设计的源程序-This is based on quartus dds source signal generator design
ADSP2011Local
- pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言。-pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at r
Quartus-II-10.1-Handbook--Volume-3
- design debugging of VHDL-the design of limited status in VHDL
i2c_master_slave_core_latest.tar
- IIC IP核，可以直接集成在SOPC中的(⊙o⊙)哦-基于Quartus II 可直接集成到SOPC，自定义II C IP核
dotdisplay
- 16*16点阵横向移动显示！采用QUARTUS II 9.0编译通过！-16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!
VHDL
- 1、根据设计要求，完成对序列信号检测器的设计。 2、进一步加强对QuartusⅡ的应用和对VHDL语言的使用。-1, according to design requirements, to complete the sequence of the signal detector design. 2, to further strengthen the Quartus Ⅱ applications and the use of the VHDL language.
fft256
- quartus ii 中利用ip核生成fft模块，实现256点fft功能-quartus ii the use of nuclear generation fft ip module to achieve the 256 point fft function
quartus-ii-9.0learn
- 用于VHDL的学习，文章内容为PDF格式简单易懂，适用于初学者-Used for VHDL study, the article content to PDF format simple and understandable, it is suitable for beginners
VHDL-language-Detailed
- 《VHDL与数字电路设计》系统介绍涉及数字系统设计的多方面原理、技术及应用。主要内容有数字系统的基本设计思想、设计方法和设计步骤，VHDL硬件描述语言，PLD的结构、原理与分类，数字系统设计开发软件平台QuartusⅡ及其使用，常用数字电路的设计方案等；涵盖现代数字系统设计完整过程的三个支撑方面；硬件描述语言、器件、软件开发平台-VHDL and digital circuit design system introduced many principles, techniques and ap
vhdl-jishuqi
- 基于quartus 2的4位二进制计数器-Based on quartus 2 of four binary counter
State_Machine
- 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state