搜索资源列表
UART
- 用VHDL编写实现的UART控制器源码,自带testbench,解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
uart
- uart接口读写控制器,已经在fpga上测试通过-uart interface to read and write controller, has been tested by fpga
uart
- uart - veiloghdl rx, tx, baudrate-uart- veiloghdl rx, tx, baudrate
UART-CPLD
- 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
uart16550_latest[1].tar
- 开源UART IP核16550,该IP核兼容16550 UART,具有Modem功能,完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
UART
- 實作UART 介面 4 byte 傳送 或 4 byte 接收 開發環鏡 quartus 且 附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
uart
- uart - universal asynchronous receicer and transmitter source code using VHDL
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
uart
- UART design with bist capability
fifouart_latest.tar
- vhdl fifo uart core datasheet
UART
- VHDL语言写的串口发送、接收程序,根据晶振和相应的波特率修改分频器就可以实现!-Written in VHDL serial send, receive, process, according to crystal and the corresponding baud rate divider changes can be achieved!
uart-txblock
- vhdl实现了UART的数据发送,将八位并行数据转成串行数据输出,并加上起始位和奇偶校验位,停止位。-vhdl UART data transmission realized, the eight parallel data into serial data output, plus the start bit and parity bits, stop bits.
ASIC_VHDL_FPGA_design_lectureNotes
- 这是美国普渡大学(Purdue University West Lafayette)ASIC design 的课件完整版!带事例和讲解的非常好的VHDL学习材料!含有vhdl 基础知识,设计步骤,UART, RTL,Test Bench 以及测试和调试,DEBUG等各种VHDL设计者必学知识!-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content inc
uart-(VHDL)
- 利用VHDL语言实现的UART串口通讯,以经过下载验证-the UART program with VHDL as develop language
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
UART
- 用VHDL实现与电脑串口进行通信。已通过开发板验证正确。开发板时钟50M,波特率19200.-VHDL implementation using serial communication with the computer. Has been verified through the development board are correct.
FPGA-UART
- 该资料是实现VHDL的串口通信(UART),RS232接口协议,-VHDL implementation of serial communication
UART
- 串口VHDL程序,Xilinxṩ 测试成功。-Serial VHDL program, Xilinxṩ test was successful.
uart-
- 通用异步通讯UART的工程文档,ISE打开工程,里面有VERILOG的源代码,可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
uart
- 一个简单的UART程序,包括接收,发送,波特率产生-A simple UART program, including receiving, sending, baud rate generation