搜索资源列表
ciper
- VHDL语言，基于Xilinx平台的电子密码锁。-VHDL language, based on the Xilinx platform of electronic locks.
FPGA_VGA_displaydoctum
- 使用 FPGA 控制 VGA 显示 相关知识介绍：包括 显示器术语 显示卡术语 VGA 时序设计 色彩原理 显示 源代码 相关测试图片-The use of FPGA control VGA display relevant knowledge, Introduction: terminology, including display graphics card design color theory terminology VGA timing related t
8051code
- VHDL源码 8051+IP内核 在xilinx环境仿真运行 不带接口的逻辑部分代码-VHDL source code 8051+ IP cores in the xilinx environment simulation to run without a logical part of the code interface
register
- this a project that makes a shift register using VHDL and the Xilinx platform. -this is a project that makes a shift register using VHDL and the Xilinx platform.
add
- is a project that achieves a Full Add with VHDL on the platform XILINX
sumador
- sumer vhdl code for FPGA of Xilinx
deinterleave
- CDMA.1X中，解交织的FPGA实现，程序基于VHDL编写，在XILINX开发板实现。-CDMA.1X, the solution of interwoven FPGA implementation, the program prepared based on VHDL, in the XILINX development board to achieve.
aips7108.tar
- SATA 仿真模型 SATA 仿真模型-Simulation Model SATA SATA SATA simulation model simulation model
adder
- adder in vhdl , ff , using xilinx ise -adder in vhdl , ff , using xilinx ise
Xilinx_3SE_Starter_Serial_Flash_v91
- sparntan 3e中基于串行flash的读写操作-sparntan 3e serial flash-based reading and writing
altpcie_64b_x8_pipen1b
- PCIE的软核程序，基于Verilog HDL语言，应用于FPGA的高级编程应用中。-PCIE soft nuclear program, based on Verilog HDL language, used in high-level FPGA programming applications.
dianzizhong
- 该代码是用VHDL编写的电子时钟，可以实现调时调分，7段码显示，在Xilinx的Spartan3E上下载测试过，压缩文件中包含了整个工程，并有管脚分配文件，非常适合VHDL的初学者，比如一些基本的按键，去抖，闪烁写法。-The VHDL code is written using the electronic clock adjustment can be achieved when the transfer points, 7 code shown to download the Xilinx
VGA
- 用VHDL语言描述的VGA显示程序，可用赛灵思公司的软件打开-Described using VHDL, VGA display program, available Xilinx' s software to open
sdramc_vhdl
- Xilinx提供的SDRAM控制器参考设计（VHDL)-SDRAM controller reference design (VHDL) designed by Xilinx
log32
- Logarithm 32 bit written in VHDL and implemented in Xilinx
dif_jiaorao
- FPGA适用的加扰和差分编码程序，VHDL描述，适用于Xilinx FPGA-for Xilinx FPGA
cangyongEDAgjzn
- 4.1 Altera MAX+plusⅡ操作指南 4.1.1 MAX+plusⅡ10.2的安装 4.1.2 MAX+plusⅡ开发系统设计入门 4.2 Xilinx ISE Series的使用 4.2.1 ISE的安装 4.2.2 ISE工程设计流程 4.2.3 VHDL设计操作指南 4.2.4 ISE综合使用实例 4.3 Lattice ispDesignEXPERT的使用 4.3.1 ispDesignEXPERT的安装 4.3.2 原理图输入方式设计
odometre
- Student project in VHDL Platform Xilinx about odometry
gj-2s
- 基于赛灵思EXCD-1的FPGA开发板，使用ISE10.1开发环境，使用VHDL语言编写，功能为计算输入方波的频率。输入方波，输出方波的频率，用数码管显示，每2s更新一次。管脚配置见工程。-Based on the FPGA Xilinx EXCD-1 development board, using ISE10.1 development environment, using the VHDL language, functions for calculating the frequency
Decoder
- A simple decoder circuit implemented in VHDL and tested on Spartan 3A Starter Kit board by Xilinx.