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RS encoder(Verilog)
- RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
verilog LDPC encoder
- 码长1536 扩展因子64的 WIMAX的LDPC 编码器，支持5/6,2/3,3/4,3个码率，需要在顶层做参数修改
encode
- 8位优先编码器。 8位优先编码器。-8-bit priority encoder. 8-bit priority encoder. 8-bit priority encoder.
8ENCODE
- 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
jpeg
- JPEG encoder in Verilog
rs_enc
- Verilog code for RS-(255,239) encoder.
verilog
- Verilog jpec coder encoder source code
viterbi
- viterbi encoder and decoder modeling verilog
reedsolomon
- reed solomon encoder synthesis and simulation is done using verilog and working fine
4x2_priorityencoder
- verilog code for priority encoder
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
11FIRfliter
- 11阶FIR滤波器和（7，4）编码器的Verilog语言，高手的作品，放心下-11-order FIR filter, and (7,4) encoder of the Verilog language, master' s works, rest assured that the next
rsencoder_latest.tar
- reed solomon encoder (255,239) verilog source code
viterbi
- verilog code for viterbi encoder and decoder
my_code
- 编码器和译码器，Verilog实现，有具体实验说明文档。-Encoder and decoder, Verilog realization of a specific experiment documentation.
hdb3_codedecode
- 用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功-Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation
verilog-encoder
- JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
anc dec
- encoder,decoder,testbench and run files
Program of 4 to 2 Encoder
- Verilog code for encoder
rs_15_11
- ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)