搜索资源列表
verilog for uart
- 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips.
xapp622.zip
- 644 MHz SDR LVDS 发射器/接收器(verilog and doc),644-MHz SDR LVDS Transmitter/Receiver
up_buhuo
- 这是一个VERILOG接收端捕获模块，扩频码32倍，可以检测到相关峰-This is a VERILOG receiver capture module ,the spreader is 32,it can test the correlation peak
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
Receiver
- UART Receiver Verilog Code
Receiver
- 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
Channel_Equalizer
- 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
Sampling_Frequency_Synchronization
- 802.11a接收机的采样频率同步源码，verilog语言的-802.11a receiver sampling frequency synchronization source, verilog language
qpsk_relate
- QPSK相关接收机及匹配接收机的verilog实现-QPSK correlation receiver and matching receiver verilog implementation
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
RS422_receiver
- UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
QPSKdigitalreceiver
- QPSK全数字接收机PDF，详细介绍了QPSK全数字接收机的构成，环路滤波器、内插器、Gardner定时恢复等部分的详细设计-QPSK digital receiver PDF, details of the composition of QPSK digital receiver, loop filter, interpolator, Gardner Timing Recovery and other parts of the detailed design
Receiver
- OFDM通信系统接收端完整verilog代码-OFDM communication system receiver complete verilog code
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
Rake_Receiver
- 用Verilog HDL语言实现一个Rake接收机的最大比合并准则，其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
verilog
- 这是一本介绍verilog语言的书籍，verilog语言应用于FPGA，可实现诸多实时处理模块，例如实时OFDM发射机和接收机的制作-verilog for FPGA，real time OFDM Transmitter and receiver
serialsimulationreciever
- serial simulation receiver in verilog
Receiver_spartn6_v1
- Implement design of UART receiver in verilog