搜索资源列表
PCIE_DMA_DDR3_verilog_design
- 基于xilinx fpga的pci-e到dma再到ddr3的数据传输完整设计-PCIE_DMA_DDR3 verilog reference design
exp6_Uart
- xilinx FPGA的rs232 Verilog HDL程序-xilinx FPGA的rs232 Verilog HDL
create_COE_file_from_vector
- Create COE for Xilinx FPGA
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
Encryption-SATA-IP-Based-on-FPGA
- 本文首先分析了目前常用的硬盘数据加密方法，并在比较各种加密方案的基础上给出了基于FPGA的加解密SATA IP设计方案。本文介绍设计SATA IP相关的基础知识，包括SATA的体系结构。本sata IP已在Xilinx spartan-6系列上实现并产品化，具有低成本优势，且可以根据用户意愿更换加密算法和使用私有的加密算法。本文还论述了加密SATA IP的各种应用前景。-This paper firstly analyzes several common ways of Hard Disk da
bram
- Xilinx FPGA内部RAM的使用实验-Xilinx FPGA internal RAM usage experiments
invaders_multi_rel0001
- XILINX FPGA 游戏实例，包括键盘控制，学习FPGA的好材料-XILINX FPGA game examples, including keyboard control, FPGA good learning materials
Desktop
- 基于xilinx FPGA的任天堂游戏机的模拟器，可以玩很多游戏，功能很强大。-Xilinx FPGA-based emulator of the Nintendo DS, you can play a lot of games, very powerful.
Txx_Pro_Flash
- xilinx FPGA ise 生成mcs文件 下载 nor flash 工具-xilinx FPGA ise generate mcs file to download nor flash tools
memory_test_edk_14p7_2
- 基于FPGA的流水灯程序，使用XILINX FPGA实现，在XPS平台上编写。压缩包是整个源工程。-FPGA water lamps procedures based on XILINX, using FPGA implementation, written in XPS platform. Package is the source project.
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
UartLoop
- xilinx FPGA XC6LX9 串口通信程序 返回发送内容-xilinx FPGA XC6LX9 serial communication program returns to send content
Xilinx_FPGA
- Xilinx_FPGA中LVDS差分高速传输的实现-Xilinx FPGA to achieve high-speed transmission of LVDS differential
DDR2_XILINX
- xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中-xilinx FPGA design needs DDR2 files that can be applied to the actual design
bmp2bin
- 将BMP图像信息转换成coe文件,用与Xilinx fpga的ROM初始化-turn the information of BMP to coe document for Xilinx FPGA
SSD_MULTIPLEXING
- four seven segment displays are in multiplexing implemented on xilinx FPGA XC3S50
dcm_1202
- 本程序是基于Xilinx的FPGA编程，运用ip核进行时钟的管理，且有测试程序。适合FPGA初学者。 -This procedure is based on Xilinx FPGA programming, using ip core clock management, and there is the test program. FPGA for beginners.
AD80305
- 一种基于xilinx FPGA S6,verilog 实现AD80305输入输出接口配置，可参考-Based xilinx FPGA S6, verilog realize AD80305 input and output interface configuration, refer to
CLK_GEN
- Xilinx FPGA时钟倍频电路，使用内部全局时钟、DCM，可参数化。-Clock Generater for Xilinx FPGA
HWL_ASYNC_FIFO_DRAM_BA
- asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.