搜索资源列表
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
comp1
- 实现了加密狗的功能，完成此功能用的硬件描述语言，verilog hdl 在各方面是最好的，欢迎下载。-fpga aes
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
AES-based-on-FPGA-jiami
- 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
AES-based-on-FPGA-jiemi
- 基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
aes
- AES FPGA verilogHDL实现(AES hardware implementation)
AESj 加密解密Verilog
- 128位AES加密解密，可以在FPGA上实现
基于FPGA的AES256位加密
- aes 256位 算法 加密程序，使用verilog 语言(AES 256 bit algorithm encryption program, using Verilog language)