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DDR_SDRAM_use_in_embedded
- 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and hi
User_manual_2410x
- This manual describes SAMSUNG s S3C2410X 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller solution in small die size
CIC_Moore
- It is a complete project of Cache Interface Controller programmed in VHDL using the logic of Moore State Machine
memory_perf
- 这是Tilera芯片的多线程示例程序，Tilera是美国一家芯片制造公司，目前已经生产出100核的芯片，此并行示例程序演示了一个单应用程序被并行执行此程序演示了不同的内存分配内存控制器和缓存的命中率。它还衡量了各种不同类型的存储器在很多情况下的性能。 -This program demonstrates the allocation of memory with different memory controller and cache homing properties. It also
1111111
- Cache控制器实验指令文件 新的实验系统的-Cache controller experimental instruction file new experiment system
ARM_l2c310
- 用于ARM11，CortexA8，CortexA9等高端ARM处理器的2级cache的详细技术文档。-AMBA Level 2 Cache Controller (L2C-310) Revision: r3p1 Technical Reference Manual.
smdk2413_application_note_rev10
- SMDK2413 (Samsung MCU Development Kit) for S3C2413X is a platform that is suitable for code development of SAMSUNG s S3C2413X 16/32-bit RISC microcontroller (ARM926EJ-S) for hand-held devices and general applications. The S3C2413X consists of 16-/32-
cache
- 基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
cache-feroceon-l2
- Feroceon L2 cache controller support driver for Linux.
cache-tauros2
- Tauros2 L2 cache controller support driver for Linux.
fsl_85xx_l2ctlr
- QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
cache-feroceon-l2
- Feroceon L2 cache controller support.
mckinley
- Tauros2 L2 cache controller support for Linux v2.13.6.
imx31-dt
- QorIQ based Cache Controller Memory Mapped Registers.
cache-tauros2
- Tauros2 L2 cache controller support.
fsl_85xx_cache_ctlr
- QorIQ based Cache Controller Memory Mapped Registers.
l2cc
- ARM L2 Cache Controller.
cache-flush-by-reg
- MN10300 CPU core caching routines, using indirect regs on cache controller.
cache-l2x0
- arch arm mm cache-l2x0.c - L210 L220 L310 cache controller support.
cachecontroller_latest.tar
- This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable address size, line size and number of cache lines - Non Pipelined architecture - No Cache f