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IP
- this a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can download it .-this is a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can dow
sourceInsight-lan
- souceinsight软件的语言解析文件，用于高亮关键字，开发浏览代码时，有所帮助。-DeviceIOControl, vc in io shows how to direct the operation of the underlying need friends can learn about.
VGA_TEST
- 用verilog HDL实现的VGA接口，调试成功，能直接使用-Implemented using verilog HDL VGA interface, debugging success, can be used directly
VGA
- VERILOG编写的VGA实验例程，包括整个工程，可以直接使用-VERILOG VGA written test routines, including the whole project, can be used directly
CoreCFI
- VERILOG编写的CoreCFI实验例程，包括整个工程，可以直接使用-Prepared CoreCFI VERILOG test routines, including the whole project, can be used directly
vga800-600
- Verilog语言实现的 VGA 显示器的 汉字和字符显示！！已经编译成功，可以直接使用-VGA monitor implementation of Verilog language and character display Chinese characters! ! Has been successfully compiled, you can directly use! ! !
verilog
- 无线通信用verilog代码，超全，可用来做基本设计-Verilog code for wireless communications, ultra wide, can be used for basic design
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
Verilog-Vending-Machine-_-georgeBlog_-A-blab-on-t
- using vending machine we can collect ice cream along with a change or can be fullfilled by any other subsequent cooldrinks
Verilog
- 在Verilog中有两种类型的赋值语句：连续赋值和过程赋值。赋值表达式由三个部分组成：左值、赋值运算符（=或<=）和右值。右值可以是任何类型的数据，包括net型和register型；但对连续赋值，左值必须是net类型的数据；而过程赋值，左值必须是register类型的数据。下面将作详细描述-There are two types in the Verilog assignment statement: continuous assignment and process assignment
Verilog-dalianglic
- verilog大量例程，大家可以下载-verilog large number of routines, you can download to see
61EDA_C1910
- ARM9架构简单CORE实现，可以综合，有实现步骤和说明，Verilog代码编写-ARM9 CORE achieve simple structure, can be integrated, with implementation steps and instructions, Verilog coding
time-counter
- 基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile
verilog
- 带同步清0、同步置1的D触发器，可以实现D触发器-0 with synchronous clear, synchronous set 1 D flip-flop, D flip-flop can be achieved
X-HDL
- 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
verilog-Streamline-tutorial
- Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构 组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模 语言。此外， Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间从设 计外部访问设计，包括模拟的具体控制和运行。-Has the following descr iption of Verilog HDL language ability: the behavior of the des
32bitcpu
- 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations righ
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
waveform
- Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形-Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform