搜索资源列表
up_buhuo
- 这是一个VERILOG接收端捕获模块,扩频码32倍,可以检测到相关峰-This is a VERILOG receiver capture module ,the spreader is 32,it can test the correlation peak
adc_verilog
- 用verilog编写的ADC控制接口,只需根据具体ADC器件的时序图修改代码就可运行。-ADC prepared with verilog control interface, just depending on the ADC timing diagram of the device can modify the code to run.
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序,已经仿真通过,可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
divider
- verilog HDL编写的浮点除法器,编译通过,可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
ARM_register
- ARM寄存器组设计的源代码,使用Verilog编程实现,可以编译仿真通过。-将中文译成英语 ARM register set design source code, the use of Verilog programming, you can compile the simulation pass.
RISC-CPU
- 用FPGA实现一个简易的CPU,采用精简指令集结构,每一条指令有16bit,高三位为指令操作数,后13位为地址,该CPU能实现8种指令操作,分别有HLT(空一个中期)ADD(相加操作)SKZ(为零跳过)AND(相与操作)XOR(异或操作)LDA(读数据)STO(写数据)JMP(无条件跳转指令)。cpu包括8个部件,分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器,各个部件之间的相互操作关系由状态控制器来控制,程序指令存放在初始rom中,本例程存放
spi
- 三线spi接口,用verilog实现,作为一个模块,可以接收并行数据,然后串行发送-Three Line spi interface, using Verilog implementation, as a module, can receive parallel data, and then send the serial
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序,可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA
DE2_115_Audio
- FPGA开发板所带的示例程序,实现音频信号的采集,处理和输出,用verilog语言编写,可直接编译下载,非常有学习和参考价值-FPGA board comes with sample programs, audio signal acquisition, processing, and output, using Verilog language can be compiled directly download very learning and reference value! ! !
dispdecoder
- verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
hdl
- 这是用Verilog HDL写的可调占空比分频控制器,可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
even_division
- 任意基数分频VERILOG代码,经过了编译,可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.
Verilog_Coding_for_Logic_Synthesis
- 可综合的Verilog编码,很不错,学习Verilog必看。不容错过-Can be integrated Verilog coding, very good, a must-see learning Verilog. Not to be missed
Verilog_VGA
- 一个是用Verilog的程序 还可以用 -One is to use Verilog procedures also can be used
FIFO
- 用VERILOG写的FIFO程序,可以直接引用经本人测试-VERILOG written using FIFO procedures, can be directly invoked by the I test
MAX-PLUSII-soft
- MAX+PLUSII软件是一个功能强大,容易使用的软件包,它可以以图 形方式、文字输入方式(AHDL、VHDL和VERILOG)和波形方式输入设计文 件,可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件,还可 以进行仿真以检验设计的准确性,下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input me
divider
- 基于Verilog的除法器设计,可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验,包括:基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ,这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写,有实验板和没有实验板的都可以用来学习。 其次还包括: FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档,很好用的文档,您下了相信不会后悔!-
fifo
- 可综合的Verilog FIFO存储器. This example describes a synthesizable implementation of a FIFO. -Can be integrated Verilog FIFO memory. This example describes a synthesizable implementation of a FIFO.
InstallFSharp
- 微软新的开发语言,可以应用于EDA.将F#变为verilog.-Microsoft s new development language, can be applied to EDA. To F# Into verilog.