搜索资源列表
DDDCCT_IDCTi
- 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包含VHDL及及Verilog版本。可用途JPEG及MEPG压缩算法 已通过测试。 -The discrete cosine transform and inverse discrete cosine transform HDL code and test files. Contains VHDL and Verilog versions. Can use JPEG and MEPG compression of algorithm has
UART_verilog
- 电脑发数据，CPLD接收后会送电脑的，verilog程序，可以直接使用-Computer to send data, the CPLD will be sent after receiving the computer, Verilog program can be used directly
adder
- 可加可减器，使用verilog编写，4位加减器。-Can be increased or decreased, verilog prepared 4 addition and subtraction.
135EGs_of_Verilog
- 135个Verilog经典程序，初学者可以多-135 Verilog classic program, beginners can see more
vds_proc
- 某知名外企公司解禁verilog代码。主要功能是视频显示处理等控制。可以综合。-A well-known foreign companies lifted the verilog code. The main function is the video display processing and control. Can be integrated.
fifo_ctrl
- 好用的fifo控制verilog源代码，供大家学习参考，可以被综合。-Useful fifo control verilog source code for the study reference, can be integrated.
firfilt
- FIR滤波器verilog源代码，经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
modetect
- 视频输入处理中的模式识别的verilog代码。经fpga验证，可以使用-Video input processing, pattern recognition verilog code. Fpga verification, you can use the
modedetct
- 功能强大的视频输入信号的模式识别verilog代码。可以综合，希望对大家有帮助-Powerful video input signal pattern recognition verilog code. Can be integrated, we hope to
vbi_proc
- 视频处理相关的verilog代码，可以实现在blank期间插入，其他有用信息。可以被综合。-Video processing, the verilog code can be inserted in the blank period, and other useful information. Can be integrated.
i2c
- 大公司解禁的I2C相关的verilog代码。可以被综合。-Large companies lifted the I2C Verilog code. Can be integrated.
led_seq_demo
- 跑马灯的打包verilog程序，包括v和ucf,以及能直接下载的xise文件-The Marquee verilog program package, including v and ucf, and can be downloaded directly xise file
filter_dds_10.29_7.2
- 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
can_verilog_IP.tar
- 运用Verilog语言编写的CAN控制IP核，符合CAN2.0B协议，仅作为参考！-CAN controller IP core using Verilog language, in line with CAN2.0B agreement, only as a reference!
IVerrilog_HDDn
- Verilog HDL入门，学习习的最好参考资料，能极短的时间内学会 -Verilog HDL entry, learning the best reference for learning, can be a very short period of time to learn to
klc_iic
- 基于I2C接口的的从机verilog代码，带子地址的发送方式，已下FPGA板子调通，大家可以借鉴。-Based on the I2C interface of the Verilog code, the tape address to send the next FPGA board tune pass, we can learn from.
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘（Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现，通过Modelsim软件对相应的波形进行仿真验证，并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be a
011-clk_div_pro
- verilog写的一个分频器，利用控制字累加方式，经测试可用-verilog to write a crossover, the control word can be used incrementally, tested
012-fre_tst
- verilog写的频率计，利用在一周期内计数方式，测试可用，500KHZ以上误差大-verilog to write the frequency meter, the test can be used
ROM_RTL
- Verilog Source File In the Quartus10.0 can be run this source code.