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COUNT
- 设计一个最大分频为225的分频器，将50MHz时钟作为输入。分频器可以通过计数器来实现，通过一个25位的计数器，然后在最后一位输出，则产生了一个最大分频为225的分频器。-Design a maximum frequency divider 225, the 50MHz clock as input. Divider can be achieved through the counter, through a 25-bit counter, and then the last one out,
0101
- Quartus II 除法器，用VHDL语言编写的.除法器。-Divider using VHDL language. Divider
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
EDA2
- 学习数控分频器的设计、分析和测试方法。数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC crossover study design, analysis and testing methods. NC divider function is that when the input given different input data, input th
div_fru
- 介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。-Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not
frenquent
- 分频器的一些程序。包括整数分频，小数分频，我感觉非常好的资料，不敢私自分享。特拿出来分享。希望想学习的好好参考下，肯定会有所感悟。-Divider of some procedures. Including the integer frequency, fractional, and I feel very good information, not privately share. Point out to share. They want to study more carefully th
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
wave
- 这里面是关于微波技术的一些试验程序，和仿真模型，主要有微带线，带状线，功率分配器，支节匹配器-This is on microwave technology, which some experimental procedures, and simulation models, mainly microstrip, stripline, power divider, branch of the matcher
fenpinqi
- 分频器的一个例子，有源代码的，希望给大家带来帮助-Divider' s an example of source code, and I hope to give us help
lowpower_dynamic_clock_divide
- Low power dynamic clock divider
div32
- 基于verilog的分频器 23分频器 可更具需要修改成任意偶数分频器-23 divider verilog-based crossover can be even more need to modify the divider into any
clk_div_n
- 时钟任意分频模块，输入为主时钟和分频数，输出为主时钟/分频数。-Clock divider
jiaocuofenpin
- 用硬件语言写了一个由8/9分频构成的无限不循环小数分频器，分频系数k=260/31-Written language with the hardware a 8/9 frequency divider consisting of an infinite non-recurring decimal, frequency factor k = 260/31
traffic
- 采用VHDL语言编写的控制交通灯工作的程序。分为四个部分：1，分频器，2，计数并产生控制信号，3，交通灯信号产生，4，交通灯总体描述。点击lzh6.aws打开工作空间-VHDL language used to control traffic lights work procedures. Divided into four parts: 1, divider, 2, count and generates control signals, 3, traffic signal generatio
VHDL
- 除法器 4位除法器 可以编程实现 有启发意义-4-bit divider divider can be programmed instructive
verilog_std_div
- Verilog HDL语言实现任意整数分频.只需调节分频数和分频位宽即可。-Verilog HDL language to any integer divider. Simply adjust the number and frequency can be frequency division-bit wide.
VHDL_fre_div
- 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of ex
sprc196
- 無傳感器控制的三相無刷直流電機（無刷直流）馬達使用梯形減刑計劃與反電動勢（反電動勢）測量獲得通過簡單的電阻分壓器。閉環電流控制採用 PID實現。-Sensorless control of a 3 phase BLDC (Brushless DC) motor using a trapezoidal commutation scheme with BEMF (Back-EMF) measurement obtained via a simple resistor divider. Closed
frediv
- EDA分频器代码vhdl例程，可用，方便理解-EDA divider vhdl code routines that can be used to facilitate the understanding of
fenpin2500
- 用VHDL写的分频器,分频大小为2500分频-Written with VHDL divider, size frequency frequency 2500