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SCdpramM.tar
- dual port RAM (modular code)
dualportram
- this is a code of dual port ram
RAM2x64C_1
- 双口RAM用于数据存储和读取，在FFT处理器重，快速的读取和存储数据，可以提高处理器速度-Dual-port RAM for data storage and reading, in the FFT processor heavy, fast read and store data, can improve the processor speed
dual_port_rom
- dual port ram, it is having two data lines and two address lines at a time we can access two data from the two data lines
m_decoder
- 恢复以曼彻斯特编码格式输入的mdi信号成实际数据并存储在双端口RAM后以中断方式通知DSP读取数据，所需双端口RAM程序可以从相应的FPGA编译系统中产生-A return to the Manchester encoded signal is input into the actual data mdi and stored in the dual-port RAM notify the DSP after the break to read the data, the required du
m_encoder
- 将写入的数据用曼彻斯特码格式从meout口输出，所需内部存储单元可根据所使用不同的FPGA类型由相应的编译软件产生所需双端口RAM模块-The data will be written by Manchester code format from meout port output, the required internal storage unit can be used according to the different types of FPGA Compiler software f
dp_ram
- 双口RAM的设计，采用Verilog HDL语言编写。-Dual-port RAM design, using Verilog HDL language.
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
ram_dp_sr_sw[1]
- dual port ram control-dual port ram control dual port ram control dual port ram control
memory_cores
- 通用ram源码包，包括双口ram，单口ram，fifo等-general ram source package，include dual port ram，single port ram，fifo，etc.
DoubleRAM
- actel fpga kit 双端口RAM 实验-actel fpga kit dual-port RAM test
dpram
- thi is a dual port ram
ram_fpgavhdl
- fpga vhdl实现一个标准双端口ram，可以作为单端口或者双端口用 -fpga vhdl achieve a standard dual-port ram, can be used as a single port or dual port with a
real_module
- 对进来的数据进行乒乓操作，例如0-63出来的结果是31-0,63-32.进来和出去为同一时钟，且都是流水线方式，结构为双口RAM.-Ping-pong on the incoming data operations, such as 0-63, the results are 31-0,63-32. Come in and out of the same clock, and are pipelined, the structure of dual-port RAM.
dsdram
- linux内核下双口ram字符设备驱动程序-dual port ram driver process under linux
ram_dp_sr_sw.v
- this is a verilog source code for Dual Port RAM Synchronous Read/Write.
dpram
- 包含整个工程，是用verilog来编写，实现双口ram的功能-Contains the entire project is to write Verilog to achieve the function of the dual-port ram
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
RAM
- 基于verilog的双口和单口RAM的实现-Verilog dual port and single port RAM-based implementation
Example-b4-1
- 1. 定制一个双端口RAM，DualPortRAM 2. 在顶层工程中实例化这个RAM 3. 实现这个工程，在Quartus II仿真器中做门级仿真 4. 在ModelSim中对这个工程进行RTL级仿真 -Customize a dual port RAM, DualPortRAM On the top floor of the RAM engineering instantiation To realize the project, in Quartus II simu