搜索资源列表
vhdlfifo
- fifo- source code for fifo using VHDL
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
TestDlg1
- USB2.0接口的设计与实现--读fifo源代码：挺好的-USB2.0 Interface Design and Implementation- fifo reading the source code: I' m fine
TestDlg2
- USB2.0接口的设计与实现--写fifo源代码：挺好的-USB2.0 Interface Design and Implementation- fifo writing the source code: I' m fine
qianru_EZWJL
- EZW举例 该源代码包含有6个文件： EZW.H － EZW编码器头文件 EZW.C － EZW编码器文件 MATRIX2D.H MATRIX2D.C － 编码器数据结果定义和数据操作 FIFO.H FIFO.C － 扫描方式定义：先入先出原则 LIST.H LIST.C － 零树结构定义和操作 UNEZW.C － EZW解码器 这里，读者重点要掌握的是EZW.C和LIST.C中的内容，充分理解零树的概念。 -EZW example of t
fifo_for_beginner
- 新手学习用的FIFO源代码，希望能帮到有用的人-Novice to learn to use the FIFO source code, useful for people who want help to
NS_control
- Code matlab for FIFO control
MGR815_v5
- Code for FIFO the first
uart
- Also the USART automatically senses the start of transmission of RX line and then inputs the whole byte and when it has the byte it informs you(CPU) to read that data from one of its registers. The USART of AVR is very versatile and can be setup
fallthrough_small_fifo_v2
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short
syn_fifo
- 很好的同步FIFO设计代码，和大家分享一下，多多交流，不是我自己写的-Good synchronous FIFO design code, and share with you some more exchanges, not my own writing
FPGA_test_frequency
- 基于FPGA的高精度测量频率的程序，里面有FIFO的子函数，代码完整-FPGA-based high-precision measurement of the frequency of the procedure, there are FIFO, Functions, code integrity
xunmi
- 操作系统课程设计_先进先出页面置换算法代码。-Operating System Course Design _ FIFO page replacement algorithm code.
HighSpeedFIFOsInSpartan-IIFPGAs
- This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be chan
xapp205_fifo_ctl
- XAPP205 Xilinx FIFO Controller VHDL code
sdfsdFifo
- 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
FIFO24_psconv
- fifo buffer vhdl code
FIFO_ise11migration
- fifo buffer vhdl code
atapi_ctl_2_5
- fifo buffer vhdl code
atapi_ctl_2_6
- fifo buffer vhdl code