搜索资源列表
NANDFlashcontrolandFIFOcontrol
- 实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码-NAND Flash control access and control of the synchronous FIFO verilog code
memChange
- 使用Qt实现的操作系统中内存管理的主要的三个算法（FIFO，LRU，OTPML），源代码中有很详细的说明，可读性很强-Uses in operating system which Qt realizes memory management main three algorithms (FIFO, LRU, OTPML), in the source code has the very detailed explanation, the readability is very strong
async_fifo
- 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
test3
- 操作系统页面置换算法的源代码，分别包含最佳置换算法，先进先出置换算法，最近最久未使用置换算法以及简单的clock置换算法。-The source code of the operating system page replacement algorithm, respectively, contain the best replacement algorithm, FIFO replacement algorithm, the most-recently-used replacement alg
Apptest
- cy7c68013写fifo速度测试的代码-the CY7C68013 write the fifo speed test code
FIFOUART
- fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
fifo_ctrl
- 好用的fifo控制verilog源代码，供大家学习参考，可以被综合。-Useful fifo control verilog source code for the study reference, can be integrated.
VFIFOzipe
- 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
aasyn_fiffos
- verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
EbbulkloopZ
- EZ-USB FX2 SLAVE FIFO模式固件代码-EZ-USBB FX2 SLAVE FIFO mode firmware code -EZ-USB FX2 SLAVE FIFO mode firmware the code-EZ-USBB FX2 SLAVE FIFO mode firmware code
fifo_lru_opt_twochance
- 请求分页虚拟存储。FIFO,OPT,LRU,二次机会。在他人的代码上修改而成。加入简单页表，逐步显示。可配置页架数，页面总数，访问序列。-Demand paged virtual storage. FIFO, OPT, LRU, second chance. Modifications made in the code of others. Added a simple page table gradually. Configurable page frame number, the total
Pbbuulksrca
- 毕业课题部分程序源码：CY7C68013 Bulk IN 68013工作在AUTO INN模式，16位总线 SLAVE FIFO.MASTER是 ADI BF533 可直接使用。 -Graduation Project part of the program source code: CY7C68013 Bulk IN 68013 work in the AUTO INN mode the 16 bus SLAVE FIFO.MASTER is ADI BF533 can be used d
UART8_Receiver
- 自己编写的带有FIFO的UART串口接收模块，代码通过状态机实现-I have written to the FIFO UART serial receiver module code by the state machine.
fifo_uart
- uart的verilog代码,包含fifo，并且采用过采样以防止噪声的干扰-uart verilog code
generic_fifos_latest.tar
- fifo的verilog代码，包含rtl，sim，testbench内容的verilog代码，完全可用-rtl code of a fifo
Nios_sram24
- 自己的毕设代码。实现用SDRAM运行nios，同时用SRAM保存摄像头数据。中间利用fifo可以保存两帧图像-Own the complete set up code. SDRAM running nios, SRAM save camera data. Intermediate use of fifo can save the image of the two
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
aFifo
- Function : Asynchronous FIFO VHDL CODE
fifo2
- 一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog
fifoVerilog
- 设计一个异步FIFO，完成数据平滑功能，FIFO的深度为256，宽度为8位，实时给出读空和溢出指示，写时钟为带间隔的100MHz，读时钟为5MHz，代码为了便于读阅，存放在word文档，可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty