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synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
source-(1)
- FIFO Algorithm Source Code
async_fifo-and-verilog
- 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
I2S
- 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
scia_loopback_interrupts
- TI F28027 SCI 源码，中断，FIFO，LoopBack使能-TI F28027 SCI source code, interrupt, FIFO and Loopback enalbe
DBfifo
- 同步FIFO设计源代码，带有复位信号的同步FIFO设计，能够在同一个时钟域范围内写入读出数据，从而做到传递数据的功效。-Synchronous FIFO design source code, synchronous FIFO design with a reset signal, can write and read data in the same clock domain range, so do efficacy data transfer.
FPGAluojidaima
- 16通道逻辑分析仪，100M，FPGA代码，包括FIFO，dram，usb等-16 channel logic analyzer, 100 m, the FPGA code, including FIFO, DRAM, usb, etc
syn_fifo_style_1
- verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
ti_master
- 这个例子显示了如何配置SSI0为TI spi模式。该代码将对主机发送三个字符，然后轮询接收FIFO，直到3个字符在主Rx接收buff空间。-This example shows how to configure the SSI0 as TI Master. The code will send three characters on the master Tx then poll the receive FIFO until 3 characters are received on the m
PIC18F_ECAN_FIFO
- Microchip Pic18F code example to enable the Mode2/FIFO example. Very little accurate information is available to enable this mode.
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
UART_RX
- 这是借鉴别人的带有FIFO的Verilog代码分享给大家，共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together
proje2
- it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
iop_fifo_in_extra_defs
- C-code for register scope iop fifo in extra for Linux v2.13.6.
Three-kinds-of-replacement-algorithm
- 本代码有三种操作系统的置换算法，分别是fifo（先进先出算法），lru（最近最少使用算法），opt（最佳置换算法），可根据需要进行选择，并计算出命中次数、缺页率和命中率等。-The code has three operating system replacement algorithm, namely fifo (first in first out method), lru (least recently used algorithm), opt (optimal replacement a
Stm32OV7670_FIFO
- ov7670-FIFO摄像头模块模组,带fifo功能，此代码是基于STM32平台实现。可以拷入开发板中直接使用-ov7670-FIFO module camera module with fifo function, this code is based on the STM32 platform. Kaoru development board can be used directly
C8051_FifoCamera(keil)
- ov7670-FIFO摄像头模块模组,带fifo功能，此代码是基于80C51单片机平台实现。可以拷入开发板中直接使用-ov7670-FIFO module camera module with fifo function, this code is based on the 80C51 microcontroller platform. Kaoru development board can be used directly
fifo_1
- 本程序是基于Xilinx的FPGA简单代码编写，对fifo的ip核进行简单的配置，并通过仿真代码进行仿真观察fifo的特性，适用于FPGA初学者。-This procedure is based on Xilinx' s FPGA simple code written for the ip nuclear fifo simple configuration, and Simulation observed through simulation code fifo for FPGA beg
uart_fifo
- FPGA与PC的串口通信代码，使用了FIFO作为数据的缓存。-FPGA and PC serial communication code, use the FIFO as cached data.
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.