设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi

a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc

here is realized simple FIFO stack in vhdl. very simple example, but very helpful.

存储器的VHDL描述，包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL