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UART.使用FPGA的FIFO，状态机
- 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。,The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
CCD.rar
- CCD数字相机的全代码，DMA方式读取FPGA，FIFO送入计算机，网口跑UDP协议,CCD digital camera the entire code, DMA mode to read FPGA, FIFO into the computer, I run UDP network protocol
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
FPGA
- 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s i
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
Fifo
- 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
fifo
- FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO
fifo_test.v.tar
- code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
fifo
- 用FPGA做的fifo，源码，调试通过，有工程和波形文件-FPGA to do with the fifo, source code, debugging through, there are engineering and waveform file
fifo
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
FIFO
- FPGA实现FIFO模块，用于异步数据处理，作为高速缓冲CACHE-FPGA realization of FIFO module for asynchronous data processing, as the cache CACHE
FIFO
- FIFO control in the FPGA-FIFO control in the FPGA
fifo
- fpga中fifo的基本原理介绍了fifo的基本原理以及对fifo实现方法的阐述。-The basic principle in fpga fifo fifo introduced the basic principles and methods of implementation described fifo.
FPGA-FIFO
- FPGA FIFO方面的相关文档，对于刚接触FPGA FIFO的同学有所帮助-The FPGA FIFO related documentation, help students new to FPGA FIFO
FIFO
- STM32通过与FPGA通信读取FPGA的串行FIFO(STM32 and FPGA FIFO communication)
DSP读写基于FPGA的FIFO
- 本文档提供了DSP对FPGA中的FIFO的读写时序以及编程思路，供大家参考。(This document provides DSP on the FPGA FIFO read and write timing and programming ideas for your reference.)