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HighResTimer
- * 一、功能: Timestamp驱动演示代码. * 二、该源码需要硬件开发板的支持,因为ISS对Timestamp定时器的模拟还不够精确 * 如果将该源码运行于ISS模式下,将得不到精确的结果 * 三、运行前提: * 1. 选择包含JTAG_UART和定时器的NiosII系统(ptf文件) * 其中的定时器要求: * (1) 具备可写的period寄存器 * (2) 具备可读的snapshot寄存器 * 2. 在系统库属性中完成下面的
JTAG_UART
- JTAG_UART的VERILOG代码
jtag_uart
- 用verilog 语言写的jtag_uart程序用于实现jtag的串口通信-Using verilog language written in jtag_uart procedures used to implement the serial communication jtag
jtag_uart
- Configuration and usage of Altera s JTAG UART.
jtag_uart
- jtag_uart实现FPGA内部和计算机之间的通信，实时监控方便-jtag_uart achieve FPGA communication between the internal and the computer, real-time monitoring convenience
jtag_uart
- SOPC jtag uart 系统集成编译的IP核-Jtag-uart IP core in SOPC
jtag_atlantic_terminal
- jtag communication between on chip jtag_uart and PC host
jtag_uart
- （2）实验2：JTAG UART通信实验，完整的设计工程文件在jtag_uart文件夹下-(2) Experiment 2: the JTAG UART communication experiment, complete design engineering the file in jtag_uart file folder
DE2-115_Basic_Computer
- BASIC COMPUTER FOR JTAG_UART