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  1. metis-5.0pre2.tar

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  2. 软件包Metis是由美国密西根大学G.Karypis和V.Kumar编写的用于图的分区和稀疏矩阵排序的串行包,提供多级k路图分区法对混合网格进行分区。-Metis package by the University of Michigan G. Karypis and V. Kumar, prepared for the graph partitioning and sparse matrix ordering of the serial package, providing multi-lev
  3. 所属分类:Data structs

    • 发布日期:2017-04-09
    • 文件大小:1.68mb
    • 提供者:flo
  1. Mail

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  2. 内部邮件服务包括email 和聊天等内容,可能对学习有帮助-Author: J.Ganesh Kumar E-mail: Click to e-mail author Website: http://www.ganeshs.freeservers.com Submitted: 9/8/2004 Version: VB6 Compatibility: VB6 Category: Networking Downloads: 6252 Thi
  3. 所属分类:WinSock-NDIS

    • 发布日期:2017-04-03
    • 文件大小:46.52kb
    • 提供者:甘继来
  1. FDM

    0下载:
  2. These files contains variety of Programs, file with ft and mkumar are basically finite difference implementation of the papers by R K pandey and Manoj Kumar. you can see the paper on science directc.
  3. 所属分类:Windows Develop

    • 发布日期:2017-04-01
    • 文件大小:7.61kb
    • 提供者:Gaurav
  1. jkandTflipflop

    0下载:
  2. this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-26
    • 文件大小:80.67kb
    • 提供者:jatab
  1. encoderdecoder

    0下载:
  2. this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year proj
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:138.76kb
    • 提供者:jatab
  1. multiplexersemultiplexer

    0下载:
  2. this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be us
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:88.66kb
    • 提供者:jatab
  1. srandDflipflop

    0下载:
  2. this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-25
    • 文件大小:200.55kb
    • 提供者:jatab
  1. addersandsubtractors

    0下载:
  2. this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code c
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:64.04kb
    • 提供者:jatab
  1. binary to gray and gray to binary code converter

    0下载:
  2. this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be
  3. 所属分类:VHDL编程

    • 发布日期:2013-10-16
    • 文件大小:59.51kb
    • 提供者:jatab
  1. da

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  2. ecgbeat.m Author - Arun Kumar A , Santhom Computing Facility Email - aka.bhagya@gmail.com 03/07/09 Program to Calculate the beats of an ECG signal Uses Continuous Wavelet Transform Data file should be a csv file - ecgbeat.m
  3. 所属分类:Communication-Mobile

    • 发布日期:2017-03-29
    • 文件大小:675byte
    • 提供者:dasu
  1. das3

    0下载:
  2. ecgbeat.m Author - Arun Kumar A , Santhom Computing Facility Email - aka.bhagya@gmail.com 03/07/09 Program to Calculate the beats of an ECG signal Uses Continuous Wavelet Transform Data file should be a csv file close all
  3. 所属分类:Communication-Mobile

    • 发布日期:2017-03-26
    • 文件大小:679byte
    • 提供者:dasu
  1. da4

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  2. ecgbeat.m Author - Arun Kumar A , Santhom Computing Facility Email - aka.bhagya@gmail.com 03/07/09 Program to Calculate the beats of an ECG signal Uses Continuous Wavelet Transform Data file should be a csv file close all
  3. 所属分类:Communication-Mobile

    • 发布日期:2017-03-31
    • 文件大小:677byte
    • 提供者:dasu
  1. mimo1

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  2. MIMO By Ashok Kumar . A.M. Zebros India
  3. 所属分类:Communication-Mobile

    • 发布日期:2017-03-28
    • 文件大小:2.08kb
    • 提供者:Ashok
  1. PROCEDURETOWORKINISE

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  2. Procedure to Work in VHDL... by Ashok Kumar . A . M Zebros India
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:3.33mb
    • 提供者:Ashok
  1. BASICVHDLCODES

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  2. BASIC VHDL DOCUMENTS BY ASHOK KUMAR.A.M ZEBROS INDIA
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:9.46kb
    • 提供者:Ashok
  1. chameleon

    1下载:
  2. Chameleon is a new algorithm in Data Mining created by Kumar. It is based on ROCK and DBSCAN algorithms.
  3. 所属分类:Graph program

    • 发布日期:2017-04-02
    • 文件大小:8.24kb
    • 提供者:lpu
  1. An_Introduction_to_Parallel_Computing_Second_Editi

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  2. 并行计算英文版电子书 基于unix操作系统的 适用于学习并行计算的相关人员作为参考-Introduction to Parallel Computing, Second Edition By Ananth Grama, Anshul Gupta, George Karypis, Vipin Kumar Publisher : Addison Wesley Pub Date : January 16, 2003
  3. 所属分类:Linux-Unix program

    • 发布日期:2017-05-21
    • 文件大小:5.99mb
    • 提供者:wenyajiao
  1. radonLikeFeaturesDemo

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  2. 该演示中包含的代码演示如何氡相似的功能,可以用来提高(以及部分)在Connectome电磁图像单元格边界。 请举出下列文件如果您发现此代码有用: Ritwik库马尔,阿梅里奥五雷纳和Hanspeter Pfister说“氡样的特点及其应用Connectomics”,接受,IEEE计算机学会研讨会在生物医学图像分析(MMBIA)2010年数学方法 http://seas.harvard.edu/〜 rkkumar radonLikeFeaturesDemo
  3. 所属分类:matlab

    • 发布日期:2017-04-01
    • 文件大小:12.44kb
    • 提供者:zhou
  1. arcs257

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  2. SYSTEM MODELLING AND PID CONTROL SYSTEM OF FOUR ROTOR HELICOPTER Author:Amit Kumar,Saurav Kumar Singh,Dipti Ranjan Biswal Abstract:Four Rotor helicopter as the name suggests has four rotors .The controls system for such a craft is complex, as it
  3. 所属分类:SCM

    • 发布日期:2017-03-31
    • 文件大小:496.32kb
    • 提供者:AMIT KUMAR
  1. 8-Bit-Up-Counter-With-Load

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  2. 8位计数器与负荷 -----------------------8位计数器与负荷 -8-Bit Up Counter With Load 1------------------------------------------------------- 2-- Design Name : up_counter_load 3-- File Name : up_counter_load.vhd 4-- Function : Up counter
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-14
    • 文件大小:4.72kb
    • 提供者:王浩
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