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uart8.zip
- 使用libero提供的异步通信IP核实现uart通信，并附带仿真程序。uart设置为1位开始位，8位数据位，1位停止位，无校验。且uart发送自带2级FIFO缓冲，占用FPGA面积很小。,libero provided the use of asynchronous communication IP core implementation uart communications, and incidental simulation program. uart is set to 1 to sta
Fusion_ABC_uart_2009_03_17
- Actel Fusion System Management Development Kit uart Example. Contains libero design using CoreABC. Program prints text to uart.
uart
- 用VHDL语言编程实现uart，8位数据位，校验位自己可以加！libero仿真正确！-VHDL language programming with uart, 8 data bits, parity bit that they can add! libero simulation correctly!
uart
- General purpose uart written in Verilog libero core generator.-General purpose uart written in Verilog libero core generator.
RX_ASYNC_for_module_uart
- Rx Async for module uart written in Verilog libero Designer core generator.-Rx Async for module uart written in Verilog libero Designer core generator.
TX_ASYNC_for_module_uart
- Tx Async fpr module uart written in Verilog libero core generator.-Tx Async fpr module uart written in Verilog libero core generator.