搜索资源列表
PLL_PLV
- 锁相回路可视为一个输出相位和输入相位的回授系统用以同步输入参考讯号和回授后输出信号。并让其操作同样的频率。如(图一)所示，简单锁相回路[3,4]是由三个电路构成，分别为相位侦测器（Phase Detector）、回路滤波器（Loop Filter）、压控荡器（VCO）-phase-locked loop can be regarded as a phase output and input phase feedback system for synchronous reference input
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
avrx
- 血凝仪检测系统,硬件电路部分由正弦波产生模块、前级放大与滤波模块、检测线圈、锁相环同步检波模块、后级平滑滤波与放大模块、AD转换器、线圈驱动模块、单片机模块等部分组成。-Coagulometer detection system, the hardware circuit sine wave generated by the module, pre-amplification and filtering module, detection coil, phase-locked loop sync
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
ADF4157
- ADF4157是ADI公司出品的一款锁相环芯片，它含有一个鉴相器，一个电子泵，一个sigma delta 分频器-ADI Corporation ADF4157 is a production of the chip phase-locked loop, which contains a phase detector, an electronic pump, a sigma delta prescaler
DesignoftrackingloopofGPSsoftwarereceiver
- 本文在分析GPS 软件接收机跟踪原理的基础上，首先比较码环与载波环不同鉴相器的性能，然后对二阶锁相环中不同环路参数设下的跟踪效果进行仿真分析，最后设计 了合适的码环与载波环路，并用实际采集的GPS 数据论证了所设计环路的有效性，为GPS 软件接收机跟踪环路的设计提供了参考。-Based on the analysis of GPS receiver tracking software on the basis of the principle, first compare the diffe
code
- it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm
PFDCP_prj
- 采用ADS对环路中鉴相鉴频器和电荷泵进行联合仿真，优化整体性能。-By ADS on the loop phase frequency detector and charge pump joint simulation, optimizing the overall performance.
dpll1600e
- 数字锁相环的设计，包括鉴相器，环路滤波器，spi口输出，分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
fast_cpda
- 一种快速的基于在弦到点距离累技术的角点检测- A Fast Corner Detector Based on the Chord-to-Point Distance Accumulation Technique 1. Find the edge image using the Canny edge detector. 2. Extract edges (curves) from the edge image: 2a. fill gaps if they are
Phase-Locked-Loop.rar
- charge pump phase-locked loop with digital phase-frequency detector,charge pump phase-locked loop with digital phase-frequency detector matalab model
DCO_ST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DPLL_TEST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
24chdetcpld
- CPLD 24个通道循环检测有时序可控制反馈回路时间差-24-channel detector has a feedback loop to control the timing
costas
- 基于costas环路的载波同步，使收发时钟频率和相位一致，环路包括四个部分乘法器和低通滤波、鉴相器、环路滤波器和数字振荡器组成-Based on the carrier synchronization of Costas loop, the frequency and phase of the transmit and receive clock is the same. The loop consists of four parts, including the multiplier and
b1
- 通过ATmel公司的mega328p芯片作为核心，使用4段移位数码管，通过usb连接电脑串口。用arduino的串口侦查器发送命令实现： 1.显示任何4位数（含小数）。 2.对改数进行末位加一（不进位）。 3.对改数进行乘十，当到达无小数点时自动变成除十，当小到无法显示自动变成乘十。 4.循环左移和循环右移（小数点位置不变）。(Through ATmel company's mega328p chip as the core, the use of 4 segment digital t
并网逆变器中全软件锁相环的设计与实现
- 讲述并网逆变器中全软件锁相环的设计与实现，，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）(and implementation of all software phase-locked loop in grid connected inverter is described, that is, detecting the positive a
4-20ma RTD
- 可测量和处理来自 2 线、3 线和 4 线电阻式温度检测器的温度信号输入，并输出与来自 RTD 输入的所处理的温度相对应的 4 至 20 mA 电流回路信号，并进行系统级的校准以提高 ADC 和 DAC 精度。(It can measure and process the temperature signal input from the 2-wire, 3-wire and 4-wire resistive temperature detector, and output the 4-20 m