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pipeline.rar
- 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧,About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
float_data_multiple_use_fixed_
- 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！,a program of float multiply, using 3-stage pipeline technology
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
mips
- 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
pipeline
- SIMULINK® MODEL FOR SIMULATION OF A 14-BIT PIPELINE ADC-SIMULINK ? MODEL FOR SIMULATION OF A 14-BIT PIPELINE ADC
simplepipeline
- 用于简单管道的水击计算，采用的特征线法。可自行修改管道参数。-For a simple pipeline water hammer calculation, using the characteristic line method. Pipeline can modify the parameters.
GPUGems1
- GPU Gems is a compilation of articles covering practical real-time graphics techniques arising from the research and practice of cutting-edge developers. It focuses on the programmable graphics pipeline available in todays graphics processing units (
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
DLXwhitcache
- 一个DLX流水线CPU的实现 附带一个两级cache的存储层次实现-DLX pipeline a CPU attached to the realization of a two-tier level of cache memory to achieve
Fire
- firestarter – A Real-Time Fire Simulator Many obstacles exist in attempting to graphically render physical phenomena that are highly fluid and ostensibly chaotic in nature. Fire is a prime example of such phenomena. Given the unrealizable compu
5.Direct3d_light
- 5.Direct 3D顶点、转换和打光处理管线。direct3d很好的教程-5.Direct 3D vertex, transformation and lighting processing pipeline. a very good tutorial direct3d
pipeline_ADC_PLL
- 该文档提出了一种应用于开关电容流水线模数转换器的CMoS预运放一锁存比较 器．该比较器采用UMC混合／射频0．18肛m 1P6M P衬底双阱CMOS工艺设计，工作电压为 1．8 V．该比较器的灵敏度为0．215 mV，最大失调电压为12 mV，差分输入动态范围为1．8 V，分辨率为8位，在40 M的工作频率下，功耗仅为24．4 ttW．基于0．18 gm工艺的仿真结 果验证了比较器设计的有效性．-A CMOS preamplifier-latch comparator used
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Pipeline
- 程序解决了给定油井位置，求出一条东西向输油管道的位置，使之到各个油井的距离之和达到最小 //程序一次性读入11组测试文件，将油井纵坐标存储在动态开辟的pipey数组里，通过运用在数组中查找第K小个元素的算法找到了管道的最优位置 //最后求得最短距离后，将最终结果一次性存储到11个输出文件中。-Program to solve a given oil well location, find a location east-west pipeline, so that the distanc
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
pipeline
- 用流水线构成的串行八位加法器，可以输出进位级联-With a line consisting of eight serial adder, can output binary cascade
urban-pipeline
- 数据结构练习。C语言解决城市管道铺设问题。某有若干区域，在一些中心区之间存在道路相连，这些道路的长度已知。现在你接到了在城市中铺设管线的任务，假设管线只能够在已有的道路下方埋设，要求管线能够到达城市的所有区域，请你提供一套铺设方案，使管线总长度最短。-Data structure exercises. C language to solve urban pipeline problems. There are a number of areas, in some way connected be
OFFPIPE A&R 2 Excel using MATLAB-E_Rev1.4-2010
- Auto-filling of Summary Result Tables of Offshore Pipeline A&R and Normal Laying Analysis using MATLAB