搜索资源列表
DDS__FPGA
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
Digitalclock_vhdl
- VHDL语言编写的数字时钟代码，环境quartus-Digital clock written in VHDL code, the environment quartusII
divide_7
- 七分频 quartus实现 有RTL图-RTL implementations seven frequency quartus map
divide_10
- 十分频 quartus实现 有RTL图-RTL is a graph realization of the frequency quartus
DFFquartus
- D触发器 quartus实现 有RTL图-D flip-flop to achieve a RTL Figure quartus
LCD1602
- 写的一个用lcd1602的随机数发生器，用的语言为Verilog，工具是Quartus II软件。-Write a random number generator with lcd1602, the language used for the Verilog, Quartus II software tool.
61EDA_C2111
- 数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。--Verilog language implementation of the digital do
DE2_Default
- 延时一个 时间通过QUARTUS环境编写VHDL代码-delay a time
RS232_ysd
- 串口接口控制器参考设计VHDL代码,方便开发FPGA人员进行串口的开发，是一个不错的源码解压安装后可在quartus里例化使用-Serial interface controller reference design VHDL code, facilitate the development of FPGA serial port staff development, is a good source decompression after installation in case of use
VGA_ysd
- vga接口控制器参考设计VHDL代码,方便开发FPGA人员进行vga的开发，是一个不错的源码解压安装后可在quartus里例化使用-vga interface controller reference design for VHDL code, and facilitate the development of FPGA vga staff development, is a good source installed after decompression in the case of usi
bancada1
- QUARTUS EXAMPLE EXPERIENCE
ula2
- QUARTUS EXPERIMENT 3
tutorialFPT101
- FPGA QUARTUS TUTORIAL HOW TO USE QUARTUS -FPGA QUARTUS TUTORIAL HOW TO USE QUARTUS
exp1
- QUARTUS EXPERIMENT EXAMPLE
top_ram
- 在quartus环境下调用ram核并对其进行功能时序仿真-ram
60
- 模为24进制计数器的VHDL语言代码，开发环境可以是Quartus 2软件-24 binary counter module VHDL language code, development environment, Quartus 2 software can be
or1200_wb_ram_gpio_pll
- Quartus ii项目，硬件平台为SOPC2000，能实现LED的各种显示控制及按键输入。包括硬件实现的Verilog及软件实现的C实现。SOPC系统的设计在Windows的quaruts ii 8.0上实现，软件部分在Ubuntu上实现。-Quartus ii project, the hardware platform for SOPC2000, to achieve a variety of LED display control and key input. Including Ver
counter
- VHDL编程的计数器，计到指定数字后就输出脉冲，Quartus软件下完整地工程文件-counter by VHDL
nixiedecoder
- 十进制数的七段译码管显示程序，在Quartus软件下的完整的工程文件，可直接运行-nixie decoder
Phonecontroller
- VHDL程序编写的电话控制器，完整地quartus工程文件，可直接运行。-the telephone controller by VHDL