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part2
- Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-se
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
t1
- 带清零和重置功能的十进制计数器，可以用LED灯显示结果-Cleared and reset with the decimal counter, can use LED lights display the results
counter
- 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
experiment4_play
- VHDL实验四，设计一个异步清零和同步时钟使能的4位加法计数器-VHDL Experiment 4, an asynchronous reset and synchronous design clock enable 4-bit adder counter
RESET-COUNTERS-scx_4300-4200
- Reset Counter printer SCX-4200-43-Reset Counter printer SCX-4200-4300
counter
- 带异步复位功能的8位二进制加法计数器的行为描述-With asynchronous reset counter 8-bit binary adder descr iption of the behavior
counter
- 这是一用VHDL语言描述的模十计数器,带复位和置数功能,希望对大家有用-This is a VHDL language descr iption of the model with 10 counters, with reset, and set the number of features, we want to be useful
General_Tools_for_Canon_printers
- Reset chip counter for Canon iP1900, iP2600, iP3600, iP4600 and MultiFunctional Peripheral MP190, MP240, MP260, MP480, MP540, MP620, MP630, MP980.
60code
- 本源代码基于VHDL语言，实现了模60的异步复位同步计数功能。-VHDL source code is based on the language, to achieve the synchronization module 60 of the asynchronous reset counter function.
Four-controllable-counter
- 功能是（用Verilog语言的，内有比较详细的注释）： （1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块). （2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块. 计数器的功能表 nclr adj_minus 功 能 0 0 复位为0 0 1 递增计数 1 0 递减计数 1 1 暂停计数 -Functi
A-Two-bits-Counter-Using-VHDL
- 两位VHDL编译计数器的简单实现，并带有异步的复位功能。-A Brief Realization of Two-bits Counter, with an Asynchronous Reset Function
The-8-down-counter-design
- 带异步复位和计数使能控制的8位二进制减法计数器设计-With asynchronous reset and the count enable control 8 bit binary subtraction counter design
YiSiWei-counter-
- 实现使能输入及异步清零的增一四位计数器，即要求在1111实现清零，且进位是1 -Realize that can input and asynchronous reset the increasing of YiSiWei counter
The-decimal-counter
- 用verilog实现的十进制计数器(异步复位)-The decimal counters (asynchronous reset)
counter
- 设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）-Design of a decimal counter module, input port,
19-TMR1-Counter-LT-10000
- 用工作于计数方式的TMR1实现按键或脉冲计数，每按键一次记录为1，可以累加和复位。-With the work in the way of counting the TMR1 key or pulse counting, every button once for a record 1, can be accumulated and reset.
RESET EPSON T50
- reset couter espon t50
programador eeprom SCX 4200
- reset counter t50 epson
Epson TX125 Reset Program
- Reset Epson TX123 waste ink pad counter