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VHDL_Development_Board_Sources
- 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
multiplyingunit
- 其乘法器原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位-Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the l
123
- 請設計一個8位元移位暫存器，規格如下： 當控制線S1，S2輸入為00時，平行載入； 當控制線S1，S2輸入為01時，在一時脈內向右shift 1位元； 當控制線S1，S2輸入為10時，在一時脈內向右shift 2位元； 當控制線S1，S2輸入為11時，在一時脈內向右shift 3位元 -Serial Adder
a_serial_adder
- 一位串行加法器，是用MAXPLUSII实现VHDL程序的编程-A serial adder is used MAXPLUSII programming VHDL implementation
Serialadder
- VHDL语言串行加法器 可以实现五位加法运算-Serial adder five addition operations can be achieved
pipeline
- 用流水线构成的串行八位加法器，可以输出进位级联-With a line consisting of eight serial adder, can output binary cascade
Case_Study_FA
- This document objective is to design a one bit full adder to be used as part of a serial adder.-This document objective is to design a one bit full adder to be used as part of a serial adder.
serial_adder
- This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
adder-VerilogHDL
- 各种加法器的VerilogHDL语言编写的包括普通加法器，串行进位加法器，超前进位加法器等-Adder VerilogHDL various languages, including ordinary adder, serial carry adder, CLA, etc.
4BitSerialAdder
- Four Bit Serial Adder
assg-5-(serial-bit-adder)
- 4 bit adder using four full adder’s structural modeling style
vhdl
- 通过VHDL语言，实现简单的多路选择器、串行加法器、并行加法器、计数器-By VHDL language, a simple multiple-choice, serial adder, parallel adder, counter
SA_VHDL-
- a simple serial adder in vhdl, enjoy it
da2c
- VHDL硬件描述语言实现DA转化-In quurtus call half adder to achieve 16-bit serial adder
adder
- 四位二进制串行加法器 VHDL语言 EPM240 数字逻辑实验-Four serial binary adder VHDL language EPM240 digital logic test
SERIALADDER
- SERIAL ADDER 8-BIT-SERIAL ADDER 8-BIT
Serial_Adder
- 注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加-Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder
src
- Digit serial adder, can be used in digital filter design You can choose the pipeline length, digit size and the word length of the adder.
serial_adder
- 串行加法器的vhdl描述，用两个移位寄存器和一个全加器，一个d触发器实现(The VHDL descr iption of the serial adder, with two shift registers and a full adder, a D trigger)