搜索资源列表
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
altera_sdram
- Simple SDRAM controller source code for Altera DE2 board
apb_slave
- AMBA 2.0 APB Example- SRAM -AMBA 2.0 APB Example- SRAM
sram64kx8
- 基于VHDL的一种SRAM模块，简单，但是可参考性强-A VHDL-based SRAM modules, simple, but can be refered strongly
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
CY7c68013_fpga_write_sram
- FPGA自FX2 slavefifo中读取数据，写入至SRAM-FPGA since FX2 slavefifo read data, write to the SRAM
NCO
- 基于FPGA和SRAM的数控振荡器的设计与实现-SRAM-based FPGA and NCO of the design and implementation
niossramflash
- 在altera FPGA ep3c25器件上实现niosii+sram+flash-Altera FPGA ep3c25 in devices to achieve niosii+ sram+ flash
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
sram_controleur_top
- Sram controller with 6 commande ports
SRAM_Control
- VHDL Code for SRAM Control (Synthesized with Synplify-Pro, Active-HDL Simulation)
EMCRTL
- RTL Code for Design of Extarnal Memory Controller for Accessing Asynchronous SRAM of size 512Kx16
memtest
- 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)
VHDLcode
- 大量VHDL程序，由浅入深包括基础程序，各种接口实验，PC、USB SRAM等扩展板实验，及综合实验设计等。-A large number of VHDL program, Deep and includes basic procedures, various interface experiment, PC, USB' SRAM other expansion board experiments, and the comprehensive experimental design.
pci9054
- PCI读写控制程序 PCI9054与SRAM连接-PCI9054 PCI read and write control procedures connected with the SRAM
sram
- 一款基于VHDL语言的静态RAM，RAM大小是128K-a kind of silence RAM
4_Low_Power_High_Performance_SRAM_Design_Using_VH
- Low Power High Performance SRAM Design Using VHDL By Mahendra Kumar, Kailash Chandra