搜索资源列表
lfsr
- lfsr.vhd - The top module in the project. lfsr_pkg.vhd - The package file used for supporting the lfsr top module. lfsr_tb - A testbench code for lfsr module. manual.pdf - A short documentation on this project. README.txt - A short descr i
Part-2-DWT-haar-using-VHDL
- Part 2 testbench for Discrete wavelet transfrom implementation in VHDL language Haar Filter
lattice_i2c
- lattice公司的i2c核rd1006 包含testbench测试模块-lattice' s i2c core rd1006 (includes test module testbench
eprom
- Verilog编写的eprom仿真模型，包括testbench文件和测试用bin文件-Write eprom Verilog simulation model, including the testbench file and bin file for testing
Multiplieur-signe
- VHDL code of a signed mixer with a testbench !
inverseuse_ex1
- this a inverse gate with lot s of other gates and testbench for novice-this is a inverse gate with lot s of other gates and testbench for novice
Cadence-Encounter
- 8x8 mulitplier. created this file using the midelsim softwre. Tested and simulated. Great waveform, so the testbench is included also. Does anybody knkow how to make a 16x16 arrray multiplier?
EE361L-Subproject0
- Testbench for the following parts found in MIPS-Parts.V
testbenchHw9-Parts-CombCirc
- // Testbench for the following parts found in // MIPS-Parts.V // * 2:1 multiplexer // * 4:1 multiplexer // * Sign extender // * ALU
testbenchHw9-Parts-Mem
- // EE 361 Hw 9 Testbench for sequential circuit Parts // * 128 word data memory and IO
testmult_top
- TESTBENCH测试程序，小数加法器的实现，小数位设为2位，将其小数位与整数位分别显示出来。-TESTBENCH test procedures, the implementation of decimal adder, is set to two decimal places, its decimal places, respectively, with the integer-bit display.
hand_shake
- 握手程序，可以完美实现跨时钟域的数据传输-handshake and testbench，verilog HDL
nco_tb
- nco的测试文件，基于altera的nco核的测试程序-nco_td altera ip core testbench
74serie-code
- 74系列的源代码 里面还包含了testbench和详细的代码说明-Prepared by flash controller vhdL source code. Contains testbench. Programming Language:VHDL, Tags:VHDL-FPGA-Verilog,
testbench_P_verilog
- 怎样编写testbench verilog-how to write testbench verilog
Writing-Testbenches-using-System-Verilog
- writing testbench in system verilog
4-bit-comparator-with-testbench
- Create a VHDL representation for a logical circuit of a 4-bit comparator. This comparator will have equal (=), smaller than (<) and larger than (>) output signals.
8051_latest.tar
- 8051 Rev 0.2 OpenCores VHDL core with testbench
rgb2yuv
- 在Altera的开发环境上，用Verilog语言实现的RGB转YUV，附有Testbench-In Altera s development environment, using Verilog language of RGB to YUV, with a Testbench
divide
- divide模块，实现除法功能。该module是用Verilog编写的，压缩包里包括了设计程序以及测试程序（testbench）。-divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).