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vhdl--timer
- 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。
VHDL-timer
- 这是关于VHDL时钟的源代码，欢迎大家下载交流！
daima.用VHDL语言设计一个数字秒表
- 用VHDL语言设计一个数字秒表： 1、 秒表的计时范围是0秒~59分59.99秒，显示的最长时间为59分59秒。 2、 计时精度为10MS。 3、 复位开关可以随时使用，按下一次复位开关，计时器清零。 4、 具有开始/停止功能，按一下开关，计时器开始计时，再按一下，停止计时。系统设计分为几大部分，包括控制模块、时基分频模块、计时模块和显示模块等。其中，计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成，其中毫秒位、十毫秒位、秒位和
stopwatch.rar
- 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可,Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
gh_timer_8254
- VHDL Source code for 8254 timer/counter
gh_vhdl_lib
- VHDL Library for 8254 timer/counter core
gh_timer_8254_081608
- Timer 8254 Verilog source code
a8254
- 自己编写的8254计数器／计时器，实现了所有的６种模式，和大家一起分享。-I have written 8254 counter/timer, realize all the six kinds of patterns, and the U.S. share.
clock
- 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
timer
- vhdl代码：电子时钟VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple
8253
- With realize based on the FPGA programmable timer counter 8253 designs -With realize based on the FPGA programmable timer counter 8253 designs
timer
- VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
miaobiao.RAR
- 实验采用七段码LED设计（数码管），显示直观；采用定时器中断，计时更准确；功能齐全，可随时启动、停止、清零，后者智能化程度更高。-Seven-Segment LED code using the experimental design (digital control), visual display using timer interrupt, a more accurate time functions, may at any time to start, stop, cleared,
Timer
- ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
jishiqi
- 24小时计时器，本计时器能够实现时分秒的精确计时(测试可用)-24-hour timer, the timer to achieve the precise time when minutes and seconds (test available)
timer
- 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
timer
- AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
timer
- 外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.