搜索资源列表
DE2_TV
- 这是一个基于DE2平台的工程,适合于初学者学习DE2开发平台的很好的工程,是用Verilog语言编写的
digitl_logic_system_Verilog
- 书中文名:线逻辑的实现:复杂数字逻辑系统的Verilog,学习Verilog一本好书!
Verilog_HDL
- Verilog HDL入门,学习的最好参考资料,可以极短的时间内学会
systemverilog
- 这是一本关于verilog编程语言的教程,对学习verilog语言有帮助
Clock
- 用Verilog 实现的电子时钟,给初学者一个模版,学习Verilog。
an_dcfifo_top_restored
- alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ,值得学习。
VERILOGHDLlanguage
- verilog HDL语言,对于超大规模集成电路开发学习非常有好处
19711Verilog
- verilog 比较基础的教程 呵呵 新手学习学习啊 大家有资料工乡
VerilogHDL
- 周立功Verilog HDL黄金参考指南,学习VerriLog的东西。
source7-8
- verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7 - 8
source9-10
- verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码,语言是:verilog 性能不错,不过资源消耗有点大,可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
risc_cpu
- 这是一个Verilog HDL编写的RISC cpu的程序,该程序共10个子程序,实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this e
adder
- 加法器(使用verilog编写的),虽然简单,但是这也是学习verilog最基础的东西!希望大家一起学习!-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
verilog_examples
- verilog的大量例子,含有常用模块,适合初学者学习。-verilog large number of examples, with commonly used modules, suitable for beginners to learn.
RTL
- 256位有符号整数乘法器,个人学习时编写,接口为IPBUS,用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
counter.rar
- 初学者学习modelsim的好例子,基于Verilog的计数器,带测试源码,在quartus2运行。,Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
Evita_Verilog
- 一个高效的FPGA学习入门软件,Evita - 互动VHDL Verilog教学程序.rar-An efficient FPGA software study entry, Evita- Interactive VHDL Verilog teaching procedures. Rar
Openrisc1200
- 开源CPU核OpenRisc1200软核Verilog代码,学习CPU首选软核-OpenRisc
yibu_FIFO_design
- 异步FIFO实例,精通verilog hdl中的例子,供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning