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同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
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verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
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异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
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SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
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本文为verilog的源代码-In this paper, the source code for Verilog
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verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
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it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
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fifo pointers in verilog gray code utilization for synchronius
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利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
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a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
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Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
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verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
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uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
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速度高达130MHz
可实现高速数据采集
程序源码为Verilog-Speeds up to 130MHz for high-speed data acquisition program source code for the Verilog
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verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
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Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
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verilog code for gray counter,synchronous and asynchronous fifo
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这是借鉴别人的带有FIFO的Verilog代码分享给大家，共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together
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VERILOG code for NOC FIFO -VERILOG code for NOC FIFO ..
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异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
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