搜索资源列表
ADC_TCL549
- Verliog语言 测试程序
6tapFIR.rar
- 6阶FIR+verliog+分布式算法（DA）,6 bands FIR+ Verliog+ Distributed Arithmetic (DA)
xapp348
- spi源码，是verliog的，有需要的可依参考进行设计自己的工程，后续有需要还有一个使用说明附上-spi-source is the verliog, reference may need to design their own projects, there is a need to have a follow-up instructions attached
rtl
- 这是FFT2048的源代码，是用verliog编写的-This is a FFT2048 the source code is written in verliog
VerilogHDL(1-7)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
VerilogHDL(8-10)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
VerilogHDL(11-13)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
electronic-clock
- Verliog HDL数字系统设计项目，电子钟。该电子钟可以实现时钟、日期、闹钟、秒表功能。-Verliog HDL digital system design projects, electronic clock. The clock can clock, date, alarm clock, stopwatch function.
rcv
- rs232 接受模块 处理 窜信号 分并信号-rs232 verliog receive module
VERLIOG
- 关于verliog建模的PDF文件，同样适宜与初学者学习-something about verliog
lcd_control
- 这个是实现LCD控制器的一个程序，用来在LCD显示器上显示数字的功能，Verliog编写-This is the realization of the LCD controller a program, used in LCD monitors displayed digital function, Verliog writing
ISP
- 用verliog语言编写简易游戏，并在ISP上运行-Verliog language to write a simple game, and running on the ISP
Experiment01
- VERLIOG 基本 LED 测试程序 适合新手-VERLIOG LED test program for novice
FPGA__uart(quartus11.0)
- 实现串口调试,也可以实现多个串口，自己建立nios核，多哥串口，带上拉电阻，以用CH340实现RS232通信-VERION verliog,qurttus 11.0 nios:nios_IDE11.0 ，
shiyan4_1
- 数码管动态扫描EDA技术与应用，Verliog语言-Digital tube dynamic scanead
4NandFlash
- fpga读写nandflash,verliog代码。16位读写，经测试。用于fpga带nandflash模块-pga read nandflash, verliog code. 16 read, tested. Modules for fpga with nandflash
verilog
- 数字信号处理的FPGA实现 第三版 verliog 从简单的加法器 到 现代滤波器-FPGA implementation of digital signal processing third edition verliog from simple adder to modern filter
dianti
- 电梯程序的设计，完成电梯从一楼到三楼的转换，用的是VERLIOG语言-Elevator program designed to complete the transition from the first floor to the third floor of the elevator, the language used is VERLIOG
sync_module
- fpga 关于verliog vga 7123的程序代码
soble
- 基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)