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除法器
- 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。 设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Descr iption Language (VHDL) Descr iption division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Pl
1.7运算器部件实验：除法器
- 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
VHDL除法器
- 用vhdl实现除法器，很好用，经过验证!
divider.8位的除法器
- 8位的除法器。用VHDL语言进行设计实现。,8-bit divider. With VHDL design languages.
div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
divider
- 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
vhd_divider
- lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器-lattice isplever7 Treasury did not divide, so the Internet to find a foreigner to write the VHDL divider
divide
- 除法器-Divider
div16
- 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
dividend4
- 本设计是一个八位被除数除以四位除数，得到不超过四位的商的整数除法器。被除数、除数、商和余数都是无符号整数。-The design is an eight dividend divided by the divisor of four, to be not more than 4 business integer divider. Dividend, divisor, and remainder are unsigned integers.
restoring
- restoring除法器设计 经典算法了，可以仿真通过-divider restoring a classical algorithm design, simulation can be adopted
chufaqichengxu
- 除法器程序，除法器模块，定点数除法的相关代码。-Divider procedures, divider module, the related fixed-point code division.
4_bit_division
- 4位除法器,文件内容为QUARTUS II支持的VHDL语言，用于做四位除法-4_bit_division
HG_chufaqi_clajiafaqi
- VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
fast_divider
- 快速除法器，采用循环移位相减算法。 已经通过仿真。-Quick divider using cyclic shift subtraction algorithm. Simulation has been passed.
division1
- 基于vhdl/verilog的18位除法器程序。已经过仿真和综合。-Based on vhdl/verilog program for 18-bit divider. Has been simulation and synthesis.
div_8
- 八位除法器 VHDL实现 八位除法器 VHDL实现-8-Bit divider 8-Bit divider 8-Bit divider
divider
- 流水型除法器，经过FPGA平台验证。宽度可以任意修改，提供计算完毕信号。-Water-type divider, after a FPGA platform validation. Width can be modified to provide the calculation is completed the signal.
divider
- 带时钟及控制的多位除法器设计，利用状态机来实现控制-multi-cycle divider design