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div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
MIPS
- 组成原理大作业--基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
SDH
- SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
Micro-program
- 微程序控制电路是CPU 控制器的核心电路，控制产生指令执行时各部件协调工作所需的所有控制信号，以及下一条指令的地址。微程序控制器的组成如图6-12 所示，主要由三个部分组成，分别是微指令控制电路、微地址寄存器和微指令存储器lpm_rom 其中微指令控制电路用组合电路对指令中的1[7..2] 、操作台控制信号SWA 和SWB 的状态、状态寄存器的输出状态FC 、FZ ，产生微地址变化的控制信号，实现对微地址控制:微地址寄存器控制电路的基本输入信号是微指令存储器的下地址字段M[6..1] ，同时还受
decoder
- 指令译码器的设计vhdl语言或者verilog HDL语言对单片机程序的处理-Instruction decoder design vhdl language or verilog HDL language processing microcomputer programs
vhdl
- 利用vhdl描述简单mcu，功能类似AVR AT90S1200的单片机的指令系统存储系统等-VHDL descr iption of the use of simple mcu, features similar to the AVR AT90S1200 MCU instruction set, such as storage systems
risc
- RISC（reduced instruction setcomputer，精简指令集计算机）是一种执行较少类型计算机指令的微处理器。改源码是vhdl语言，能在FPGA上跑。-RISC [reduced instruction setcomputer, Reduced Instruction Set Computer] is an implementation of fewer types of computer instructions to the microprocessor. VHDL s
CPU
- RC4 Encrpytion 1.Encrpyt strings 2.Create pairs of keys for encoding and decoding automatically 3.Present the crptograph 4.Decode the crptograph to get the plaintext -This CPU has basic instruction set, and we utilize its instruction set
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
ee721_project
- has the code of instruction decoder of 8085 .. Not all functions are present only partial code is available.. Comments are welcome
cpu
- 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
MANIK
- MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density ̶
single_cycle_16bit_computer
- This single cycle 16-bit computer with testbenches written in Verilog. It shows a result based on the instruction memory. I also included documents about the structure of the single cycle computer-This is single cycle 16-bit computer with testben
VHDL
- 基于VHDL设计的通用实验CPU中译码器部分，用于进行指令译码。-VHDL design of experiments based on general-purpose CPU in the decoder part, used for instruction decoding.
DS18B20
- 8位单片机与DS18B20并行双向通信。 Quartus II 8.1项目工程文件. 主源程序文件为DS18B20.v,里面有详细注解。 例子： DS18B20 数据地址 0xf000（ROM=0） DS18B20 ROM指令地址 0xf001（ROM=1） 外部电源供电且只有一DS18B20的读取法： 发送CC到0xf001, 等待busy=0说明器件已准备好, 读0xf001的Bit1=1说明存在器件,Bit0=1为控制忙(可以省略此步） 发送44
RISC
- RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine
Staged-Output-Of-IJVM-By-VHDL
- IJVM by VHDL.IJVM is an instruction set architecture created by Andrew Tanenbaum for his MIC-1 architecture. It is used to teach assembly basics in his book Structured Computer Organization.
HardwareDesignAndModeling
- instruction vhdl persian