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Viterbi_IP.rar
- viterbi译码器的IP核，可以直接编译使用,viterbi decoder IP core, the compiler can directly use
viterbi.rar
- 这是一个用VERILOG HDL语言编写的viterbi译码程序,This is a language VERILOG HDL by the viterbi decoding process
viter2
- verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Viterbi
- 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Viterbi
- Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
viterbi
- 一个vitrtbi算法的参考实现,verilog的-A reference implementation vitrtbi algorithm, verilog of
urn_nbn_se_liu_diva-6949-1__fulltext
- Viterbi decoder algorithm
VB_decode
- Viterbi译码的VHDL代码，并且附有详细说明-Viterbi decoding of the VHDL code, and accompanied by a detailed descr iption
Viterbi_decoder
- Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog
viterbi5
- implemented viterbi in vhdl
diff_viterbi_decode
- viterbi 译码，不是个人随便写出的东西到处乱发，是公司内部产品-viterbi decode
viterbi
- viterbi decoder with convolutional encoder
viterbi
- verilog code for viterbi encoder and decoder
79419138ViterbiFPGA
- Viterbi algorithm is used for Forward Error Correction codes for wire less communication net works.-Viterbi algorithm is used for Forward Error Correction codes for wire less communication net works.
viterbi-3.0.1
- 前向纠错viterbi-3.0.1的实现 测试通过-FEC viterbi-3.0.1 implementation tested
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
viterbi
- 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.