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MIPS五级流水线模拟程序
- MIPS五级流水线模拟程序，能执行简单的MIPS指令，模拟流水线状态及寄存器结果，实现cpu流水的概念-MIPS five-level stream-line simulation program, this program can execute simple MIPS instruction, simulat stream-line s status and register result, and it implements stream-line of cpu.
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
DLXwhitcache
- 一个DLX流水线CPU的实现 附带一个两级cache的存储层次实现-DLX pipeline a CPU attached to the realization of a two-tier level of cache memory to achieve
6_seg_cpu
- 我写的6段流水线cpu，供大家参考。里面包括了alu memory topcpu等模块-I wrote a six-stage pipeline CPU, for your reference
CPU
- 32位精简指令处理器 非流水线版 具有无极流水线-32bitRISK CPU without pipeline
071221088
- 实现一个简单的单周期流水线CPU，使用verilog语言开发 在quartus平台下运行-Implement a simple single-cycle pipelined CPU, using verilog language development platform running in quartus
061110061
- 在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令-Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions
pipeline_test
- 流水线CPU,将指令的运行分为五个段，这是个五段流水线-pipeline CPU
x
- 某五级流水线CPU的设计原理图，含基本输入输出控制-traditional pipelined CPU design
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
cpu
- MIPS流水线CPU的工作原理和设计方法-The design and implementation of the pipelined CPU
pipelined-CPU
- verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
CPUv1.6
- 简单的流水线CPU 课设做的 有实验报告 跟设计图-Simple pipelined CPU Lesson set up a lab report with design
logic-design-of-CPU
- 本文献介绍了基于32位架构的双发射流水线设计。-design of 32bits CPU
CUP
- 流水线cpu，简单的CPU，但是功能俱全-Pipeline cpu
VHDLCode_8bitCPU
- 这是计算机组成原理的课程设计，将16位CPU改造成8位流水线CPU，AHDL语言，这是改造完成的源代码。-This is a computer composition principle of curriculum design, the 16-bit CPU transformed into eight pipeline CPU, AHDL language, which is the transformation was complete source code.
cpu
- 16位五级流水线CPU no cache-16 five pipelined CPU no cache
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
p5_clean
- 支持20条指令的五级流水cpu，北航计算机组成p5实验(A five level pipelining CPU that supports 20 instructions)