搜索资源列表
check_sum
- 计算校验和 校验和算法描述:为保证网络上传输的数据的可靠性,在许多协议中都设置了校验和项,例如:IPv4、ICMPv4、IGMPV4、ICMPv6、UDP和TCP 等等。计算这些校验和的算法称为网际校验和算法,简单来说就是:把被校验的数据16位进行累加,然后取反码,若数据字节长度为奇数,则数据尾部补一个字节的0以凑成偶数。 由于从输入文件读入的数据不能直接满足计算校验和的条件,所以首先对从文件读入缓冲区的数据进行预处理,即读入缓冲区时忽略空格。由于累加是按16位进行的,所以每次从缓冲
1000counter
- 在US-2中用汇编实现的一个1000进制的计数器.我本人写的,验证可用.有不明处可以联系:gracequanliang@126.com
counter24
- 通过硬件描述语言编程实现了计数器,可以实现二十四进制的数-Through hardware descr iption language programming to achieve the counter, can achieve a few 24 M
menglongyu30
- 模为12计数器 时钟电路需用到,能实现12进制的计数-Counter mode clock circuit 12 may need to rely on, to achieve a count of 12 hexadecimal
cnt_100
- 带有同步复位的可加载的100制进的可加可减计数器-With synchronous reset can be loaded into the 100 system can be increased or decreased Counter
kn_cnt256
- 此程序实现的是可逆计数器,通过对外部引脚的设置,何种进制。 -Realization of this process is reversible counter, through the external pin settings, what kind of band.
jian23
- 一个最基础的23进制减法计数器,与加法想类似!-One of the most 23 hexadecimal subtraction based counters, and would like to add a similar!
jiushuqi_10
- 一个计数器,十进制的。读者可以通过修改其中的一些参数,将十进制改为其他的进制-A counter, decimal. Readers may amend some of these parameters will be replaced by other binary decimal
calc
- 一个在VC6.0做的多功能计数器,可以实现各种进制的转换等各种复杂的功能-VC6.0 to do a multi-function counter, can achieve a variety of binary conversion, and other complex functions
count4-gates
- 4进制源码计数器。用vc中调用systemc做的。-systemc vc
zonghe
- 实现12进制异步计数器,内置分频模块,可以下载到单片机上查看结果-12 hex asynchronous counter, built-in frequency module, can be downloaded to view the results on the single-chip
Counter
- 计数器,五进制的计数器,在此基础上可以做十进制,六十进制等的计数器.-Counter quinary counter, can be done on the basis of the decimal, six decimal, such as the counter.
jishuqi
- EDA实现计数器功能十六进制和二十四进制-EDA counter function hex and 24 quaternary
Eight-16-band-frequency-meter-design
- 8位16进制频率计的设计,其中包括测评控制电路的设计,32位锁存器的设计,32位计数器的设计和频率计顶层文件-Eight 16-band frequency of the design, including the design of the evaluation of the control circuit, 32-bit latch design, the design of 32-bit counter and frequency meter top-level document
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器,利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa
scommtest
- VC++版串口调试助手源码,功能还是比较多的,接收区和来显示串口消息,在调试时,可指定串口、波特率、校验位、数据位、停止位,关闭串口和清空接收区、以十六进制调试、保存显示数据、在同一周期后自动发送数据、选择发送文件、计数器清零等功能,代码在VC++6.0中可直接编译。-VC++ version of the serial debugging assistant source, function, or more, reception area and to show the serial mes
count15
- 用verilog语言实现15进制加法计数器的功能-Achieve 15 binary adder counter function using verilog language
UART
- system C编程实现16进制可逆计数器-system C programming counter