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asic_final
- Verilog 程序 实现一个简单的语音信号增强DSP设计 分为左右声道-To realize a sound de-nosing dsp using verilog
zixiechengxu
- 用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，-Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
emif_tt
- 实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding
FPGA_DSP
- 《FPGA数字信号处理与工程应用实践附光盘》配套源代码-FPGA DSP and their applications with verilog HDL