搜索资源列表
ref-sdr-sdram-verilog
- sdram控制器的开发程序，还有文档，可以参考以下
sdr_sdram_control
- 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
sdram_all
- sdram 控制器的verilog 实现，包括用户逻辑和控制器的设计-SDRAM controller Verilog realization, including user logic and controller design
sdram
- 在ISE开发环境下的单速率SDRAM简单读写控制器设计，用的是verilog硬件描述语言-ISE development environment in a single-rate SDRAM controller read and write simple design, using the verilog hardware descr iption language
FPGAbasedSDRAMControll
- 基于FPGA的SDRAM控制器 Realization FPGA-based SDRAM Controller with Verilog-FPGA-based SDRAM Controller Realization FPGA-based SDRAM Controller with Verilog
mt48lc4m32b2
- SDRAM module Verilog HDL-SDRAM module Verilog HDL
ddr-sdram-verilog-resource
- 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-descr iption the resource code of ddr_sram
sdram-ctrl
- FPGA sdram 全页模式控制，用verilog语言写的，非常的精简，控制方便-FPGA sdram full-page mode control, written in verilog language is compact, easy to control
SDRAM_verilog
- 关于FPGA控制SDRAM笔记详细的资料，verilog写的程序，注释也很详细，值得参考。-FPGA control SDRAM notes detailed information, the program written in Verilog, comments are also detailed, it is also useful.
DDR-SDRAM
- ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
sdram_mdl
- SDRAM的verilog程序控制模块，希望对大家有帮助-SDRAM verilog program control module, we want to help
SD_SDRAM_LCM_PROJECT
- verilog控制SD卡与SDRAM之间数据传输及LCM显示，希望对大家有帮助-The verilog Control SD card with SDRAM between data transmission and LCM hope everyone
eetop.cn_SDRAM
- 实现sdram控制器的verilog代码，很好的学习资料-The sdram controller verilog code, very good learning materials
sdr_ctrl
- SDRAM控制器源码 Verilog描述-SDRAM controller Verilog source descr iption
lpddr_verilog_model
- 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
MICRON_2048Mb_ddr2
- micron ddr2 sdram verilog model and documents
DDR3-SDRAM-Verilog-Model(1)
- contains the information and codes of DDR3 memory model
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
SDRAM
- SDRAM controller: it contains a SDRAM controller writtern in verilog language. It is a interface between microprocessor and SDRAM device.
S27_SDRAM_IP
- SDRAM 驱动读写demo，用verilog写的上板测试过-SDRAM verilog