搜索资源列表
VHDL_clock
- 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Trafficlight
- 系统设置一个两位BCD码倒计时计数器(计数脉冲1HZ),用于记录各状态持续时间; 因为各状态持续时间不一致,所以上述计数器应置入不同的预置数; 倒计时计数值输出至二个数码管显示; 程序共设置4个进程: ① 进程P1、P2和P3构成两个带有预置数功能的十进制计数器,其中P1和P3分别为个位和十位计数器,P2产生个位向十位的进位信号; ② P4是状态寄存器,控制状态的转换,并输出6盏交通灯的控制信号。-System to set up a two BCD code c
shiyan6
- 一个8位的十进制频率计数器,功能经过测试.-An 8-bit decimal frequency counter, function tested.
q
- 数字钟是一个将“时”“分”“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时;显示满刻度为23时59分59秒,另外具备校时功能和报时功能。因此,一个基本的数字钟电路主要由“时”“分”“秒”计数器校时电路组成。将标准秒信号送入“秒计数器”,“秒计数器”采用60进制计数器,每累加60秒发送一个“分脉冲”信号,该信号将被送到“时计数器”。“时计数器”采用24进制计数器,可实现对一天24小时的累计。译码显示电路将“时”“分”“秒”计数器的输出状态六段显示译码器译码。通过六位LED七段显示器显示出
jietifangbo
- 用计数器来完成阶梯拨程序设计以及方波的程序设计-With counters to complete the ladder as well as the allocation of programming procedures square design
clock
- 60进制计数器,采用十分简便的方法,能够很快速的完成计数功能。-60 M-ary counter, using a very simple way to very quickly complete the count function.
DVF
- 数控分频器的设计数控分频器 端口定义: CLK:时钟输入 D[7..0]:预置数据 Fout:分频输出 说明: D[7..0]作为8位加1计数器的初值,初值越大,分频输出频率越高,反之越低, -NC NC divider divider port the definition of design: CLK: Clock input D [7 .. 0]: preset data Fout: frequency output that: D [7 .. 0] as
24
- 简单的数字时钟EDA设计,并通过电路的仿真和硬件验证,进一步了解计数器的特征和功能。-Simple digital clock EDA design, and through circuit simulation and hardware verification, and further understanding of the characteristics and functions of counters.
DDSckkc
- 以把直接数字频率合成(DDS)看成这样一种技术,它能用数字值形式的信号控制正弦波的频率。最简单的DDS电路包括一个二进制计数器,一个以等间隔正弦波值进行全波编程的ROM,以及一个数模转换器,用于将存储的正弦波值转换为电压。计数器的时钟频率决定了正弦波的频率,但这 -To the Direct Digital Synthesis (DDS) as such a technology, it can use the digital value of the form of the frequen
vhdl
- 100进制计数器的设计 -100 binary counter design
8sfdsd
- 用VHDL实现的八位可逆计数器,可作为交流学习使用。-VHDL implementation with eight reversible counter can be used as the exchange of learning to use.
clk_div
- 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
adder
- 基本组合电路 含异步清零和同步时钟的加法计数器-Basic combinational circuits with asynchronous clear and the addition of synchronous clock counter
counter_bcd7
- bcd十进制计数器,用于频率计设计的计数器单元,输出zeros用于选通量程使用!-bcd decimal counter, the counter for frequency counter design unit, the output zeros for the use of strobe range!
frequencymeter
- 测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速,以及便于实现测量过程自动化等优点,是频率测量的重要手段之一。-Measuring the frequency of means, including electronic counter to measure frequencies with high precision, easy to use, fast measurement and easy to realize the advantages of automa
source
- 几个小程序的合集,有十进制计数器、三相电机、电子钟等,对VHDL新手比较有用-Collection of several small programs, there are decimal counters, three-phase motors, electronic clock and so on more useful VHDL novice
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
VHDL
- 四选一电路,分钟计数器,三八译码器,先进先出-Four elected a circuit, VHDL procedures VHDL procedures VHDL procedures VHDL program
vhdl
- 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
plj
- 使用vhdl语言原件例化设计数字频率计,并用6位7段数码管计数。模块包括:十进制计数器,6位10进制计数器,Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6