搜索资源列表
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
VFIFOzipe
- 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
aasyn_fiffos
- verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
fifo
- 同步fifo的verilog代码，很好的资料，值得学习-Synchronous fifo verilog code, very good information, it is worth learning
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
async_fifo
- 异步FIFO verilog 代码 复位到空，读侧以及写侧复位均可以使两侧同时复位，且基本同时放开。-ayschronized FIFO verilog code
sync_fifo
- Verilog HDL code for synchronous SRAM FIFO