搜索资源列表
risc
- 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
verilog2
- 本代码在Quartus II 9.0 (32-Bit)环境编译运行，使用SOPC_NIOSIIFPGA开发板，可作为入门级代码讲解，将50MHZ的频率改为1MHZ，并以此频率为基准计数显示在七段数码管上。（采用verilog语言）-The code in Quartus II 9.0 (32-Bit) environment to run the compiler, the use of SOPC_NIOSIIFPGA development board, entry-level code ca
071221088
- 实现一个简单的单周期流水线CPU，使用verilog语言开发 在quartus平台下运行-Implement a simple single-cycle pipelined CPU, using verilog language development platform running in quartus
061110061
- 在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令-Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions
DE2_Default
- DE2开发板 verilog语言描述 Quartus II环境-DE2 development board verilog language to describe
led
- quartus 工程 测试硬件LED Verilog 源码-the quartus engineering test the hardware LED Verilog source
digital_clock
- QUARTUS中实现数字钟，有计时计分计秒的功能，整点报时的功能，用VERILOG实现。-QUARTUS achieve digital clock, a timer function scoring the seconds, the whole point timekeeping function, using VERILOG implementation.
11223
- 通过使用EDA工具，设计实现简易音乐播放器。在结合各个数字功能模块并利用FPGA系统本身丰富的物理资源的同时，将音乐的乐谱设计在FPGA内部，在Quartus II环境下，采用Verilog HDL 语言实现音乐合成器和播放系统。-By using EDA tools, design and implementation simple music player. The integration of the various functional modules and the use of F
car
- 运用Verilog语言，用quartus及niosII的的开发环境，实现了出租车计费器的设计-Using Verilog language, using quartus and niosII the development environment, to achieve a taxi meter design
div
- 这是我用verilog写的一个电平触发的一个除法器，文件在压缩包内，开发环境是Quartus II。-this is a file of divide using verilog language.
Digital-clock
- 本程序是用QUARTUS软件设计的数字钟，采用verilog语言描述-This procedure is to use the QUARTUS software design of digital clock, using verilog language descr iption
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
emif_tt
- 实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding
bit7_Binary_to_BCD_LED
- 二进制转十进制BCD码 Verilog语言 quartus-Binary to decimal BCD code Verilog language quartusII
88RISC-CPU
- cpu设计能在quartus上运行 用verilog语言-a cpu program use verilog on quartus
yuandaima
- 以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境-GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II
swp
- 本文用Verilog语言设计实现SWP数字收发接口的电路设计，并用QuartusⅡ9.1完成调试和功能仿真。在我们的设计中，采用的是分模块的设计方法。设计过程中，我们将首先完成系统架构设计，明确各个分模块的功能。分别实现各模块功能后，再联合所有模块进行总体系统的调试和仿真，最终完成SWP数字收发接口的模块设计。-SWP paper implements digital transceiver interface circuit design using Verilog language desi
heart-rate-meter
- 使用quartus II软件，verilog 语言，用来测试脉搏跳动次数，有单片机接口代码-Use quartus II software, verilog language, used to test the pulse beats, there are single-chip interface code
4x4 Keypad
- 用Verilog实现的4*4键盘扫码程序，在quartus平台实现。(Use Verilog implementation of 4 * 4 keyboard scan code program, realized in quartus platform.)
LCD1602
- 用Verilog实现的液晶显示屏程序，在quartus平台上测试成功。(Use Verilog implementation of LCD display program, on quartus platform test successfully.)