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小学生加法器设计
- java小应用程序开发，小学生加法器实现，包含友好界面，过程简洁，算法详细。-small application development, students achieve Adder, including friendly interface, simple process, the algorithm in detail.
adder
- 多位数加法 多位数加法 -More than the median more than the median adder adder adder more than the median
fulladder
- full adder. dai jinwei de liangwei quan jiaqi-fulladder
a_serial_adder
- 一位串行加法器，是用MAXPLUSII实现VHDL程序的编程-A serial adder is used MAXPLUSII programming VHDL implementation
adder
- this code written in systemc language and it is a wewest language that important to simulate the system
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
save_adder
- implement of carry save adder with verilog
lookahead
- implement of carry look ahead adder vith verilog
adder
- full adder implementation
adder
- 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
fpadd
- Floating point adder
adder
- 此程序是用verilog语言编写的8位加法树乘法器，这种乘法器速度快，可以实现一个周期输出一个结果…-This program is written in verilog language 8-bit adder tree multiplier, the multiplier speed and the ability to achieve a cycle of output of a result ...
adder
- 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
adder
- adder的程序代码！！希望需要的人下载！-adder of code! ! Hope that those who need to download! 11111
Adder-Contraction-and-expansion-
- 对话框文本文档中加法器+收缩扩展按钮+点击文本变化。 程序运行正确，环境为VS2010 程序中中含有注释和具体步骤 -Dialog text document adder+ contraction expansion button+ click the text change.The program is running correctly, the environment for VS2010Program contains notes and the specific
adder
- 实现各种加法器的功能，包括4位及8位超前进位，4位及8位逐次进位加法-The various adder functions, including four and eight lookahead, 4-bit and 8-bit successive-carry adder
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
32bit-adder
- 用hspice软件写完成的32位加法器,可以完成2个32bit数组的加法运算-32bits adder for hspice
Adder
- VHDL code for 4bit adder and full/half adders